參數(shù)資料
型號： MC56F8123VFBE
廠商： Freescale Semiconductor
文件頁數(shù)： 124/140頁
文件大小： 0K
描述： IC DSP 16BIT 40MHZ 64-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 27
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
56F8323 Technical Data, Rev. 17
84
Freescale Semiconductor
Preliminary
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
Reset Mode, which has two submodes:
— Total Reset Mode
– 56800E Core and all peripherals are reset
— Core-Only Reset Mode
– 56800E Core in reset, peripherals are active
– This mode is required to provide the on-chip Flash interface module time to load data from Flash
into FM registers.
Run Mode
The primary mode of operation for this device, in which the 56800E controls chip operation
Debug Mode
56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and PWMs,
continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor from
being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
Stop Mode
56800E, memory, and most peripheral clocks are shut down. Optionally, the COP and CAN can be stopped.
For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before
entering Stop mode, since there is no automatic mechanism for this. The CAN (along with any non-gated
interrupt) is capable of waking the chip up from Stop mode, but is not fully functional in Stop mode.
6.4 Operating Mode Register
Figure 6-1 OMR
The reset state for MB will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. The EX
bit is not functional in this device since there is no external memory interface. For all other bits, see the
56F8300 Peripheral User Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NL
CM
XP
SD
R
SA
EX
0
MB
MA
Type
R/W
RESET
0
0000
0
X
0
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