參數(shù)資料
型號: MC56F8123VFBE
廠商: Freescale Semiconductor
文件頁數(shù): 7/140頁
文件大小: 0K
描述: IC DSP 16BIT 40MHZ 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 27
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8323 Technical Data, Rev. 17
104
Freescale Semiconductor
Preliminary
8.3 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOX_PUR and
GPIOX_PER registers change from port to port. Tables 4-21 through 4-23 define the actual reset values
of these registers.
Part 9 Joint Test Action Group (JTAG)
9.1 JTAG Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
GPIOB7
PHASEA0 / TA0
52
Quad Decoder 0 register DECCR is used to select between
Decoder 0 and Timer A
Quad Decoder is NOT available in 56F8123
GPIOC0
EXTAL
46
Pull-ups default to disabled
GPIOC1
XTAL
47
Pull-ups default to disabled
GPIOC2
CAN_RX
61
CAN is NOT available in 56F8123
GPIOC3
CAN_TX
62
CAN is NOT available in 56F8123
GPIOC4
TC3
63
GPIOC5
TC1 / RXD0
64
SIM register SIM_GPS is used to select between Timer C and
SCI0 on a pin-by-pin basis
GPIOC6
TC0 / TXD0
1
SIM register SIM_GPS is used to select between Timer C and
SCI0 on a pin-by-pin basis
Table 8-3 GPIO External Signals Map (Continued)
GPIO Function
Peripheral
Function
Package
Pin
Notes
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