參數(shù)資料
型號: MC16V1CPU20B1
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 66/128頁
文件大?。?/td> 571K
代理商: MC16V1CPU20B1
MOTOROLA
MC68HC16V1
42
MC68HC16V1TS/D
3.6.1 Background Debug Mode Operation Out of Reset
Unlike M68HC16 family derivatives using a system integration module (SIM) or single-chip integration
module (SCIM) that dedicate specific pins to support CPU16 background debug mode (BDM) operation,
the SLIM allows the DSO, DSI, BKPT/DSCLK, and FREEZE signals to also serve as port D general
purpose I/O lines (PD[3:0]). The BKPT/DSCLK signal must be driven appropriately during reset to con-
figure port D for BDM operation. Table 21 shows the configuration port D BDM signals during reset.
3.6.2 Default Configuration Override During Reset
Default reset values for some bits in the PCON and MCRC shadow registers can be overridden by driv-
ing specific pins to predefined logic levels during reset when the DRCD pin is driven to logic 0. The fol-
lowing paragraphs describe the different default configuration override options.
3.6.2.1 MCU Operating Mode
The default MCU operating mode can be overridden during reset by driving the DS, SIZE, and R/W pins
to the states shown in Table 22.
3.6.2.2 Port C Configuration
The default configuration of PC[1:0] and ADDR[17:16] can be overridden by driving the ADDR/DA-
TA[3:1] pins to the states shown in Table 23.
Table 21 Port D Reset Configuration
BKPT/DSCLK
Port D Configuration
0
PD[3:0] provide background debug mode lines
1
PD[3:0] provide general-purpose I/O lines
Table 22 Default Operating Mode Override
Shadow Bits
DS
SIZE
R/W
Operating Mode
MCRC[11:9]
0
X
Reserved
1
0
Expanded non-multiplexed
1
0
1
Expanded multiplexed
1
X
Single chip
Table 23 Port C Default Configuration Override
Shadow Bit
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
Pin Configuration
PCON[13:11]
0
PC[1:0]
0
1
PC1, ADDR16
0
1
0
ADDR[17:16]
0
1
Reserved
1
X
Reserved
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