參數(shù)資料
型號： MC16V1CPU20B1
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100
封裝： TQFP-100
文件頁數(shù)： 51/128頁
文件大?。?/td> 571K
代理商： MC16V1CPU20B1
MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
29
SLPC — Software Watchdog LPSTOP Count Select
0 = Software watchdog does not count in LPSTOP; counting is resumed after reset.
1 = Software watchdog counts in LPSTOP.
RZ — Timer Zero Flag
This bit is set after the RTC downcounter reaches zero. Clear the bit by reading the register with the RZ
bit set to one, then writing the RZ bit to zero.
SZ— Software Watchdog Zero Flag
This bit is set after the software watchdog downcounter reaches zero. Clear the bit by reading the reg-
ister with the SZ bit set to one, then writing the SZ bit to zero.
IRSEL — Interrupt/Reset Select
This bit selects whether the software watchdog downcounter issues a reset or an interrupt upon count-
ing down to zero.
0 = Counter issues reset
1 = Counter issues the interrupt designated by TIQL[2:0]
TIEN — Timer Interrupt Enable
This bit controls whether the real-time down counter issues an interrupt after a timeout.
0 = No interrupt is issued upon reaching zero
1 = Interrupt is issued upon reaching zero
TIQL[2:0] — Timer Interrupt Request Level
This field defines the priority of the interrupt that is generated when the real-time down counter or the
software watchdog down counter time out. Refer to Table 12.
HME — Halt Monitor Enable
The HME bit controls the halt monitor as it checks for double bus faults on the IMB.
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor Enable
The BME bit enables the internal bus monitor for internal to external bus cycles. It can be written only
once after reset.
0 = Disable bus monitor function for internal to external bus cycles.
1 = Enable bus monitor function for internal to external bus cycles.
BMT[1:0] — Bus Monitor Timing
This bit field selects the time-out period in system clocks for the bus monitor. It can be written only once
after reset. Refer to Table 13.
Table 12 Timer Interrupt Request Level Field
TIQL[2:0]
Description
0
Interrupt Disabled
0
1
Interrupt Request Level 1
0
1
0
Interrupt Request Level 2
0
1
Interrupt Request Level 3
1
0
Interrupt Request Level 4
1
0
1
Interrupt Request Level 5
1
0
Interrupt Request Level 6
1
Interrupt Request Level 7
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