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| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 64/128頁(yè) |
| 文件大小： | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
40
MC68HC16V1TS/D
3.5.13 Misaligned Operands
The CPU16 processor uses a basic operand size of 16 bits. An operand is misaligned when it overlaps
a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even address), the
address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address is on a byte
boundary only. A byte operand is aligned at any address; a word or long-word operand is misaligned at
an odd address.
The CPU16 can perform misaligned word transfers. The CPU16 treats misaligned long-word transfers
as two misaligned word transfers. Misaligned transfers entail a substantial performance penalty.
3.5.14 Operand Transfer Cases
Address and data buses, which can be either multiplexed or non-multiplexed, and various control sig-
nals, bring about the transfer of data between the EBI and external devices. Signals issued by the bus
master control data movement across the bus within an asynchronous bus structure.
Table 20 is a summary of how operands are aligned for various types of transfers. OPn entries are por-
tions of a requested operand that are read or written during a bus cycle and are defined by SIZE and
ADDR0 for that bus cycle.
Using external logic, the SIZE and ADDR0 signals can be decoded with an active low chip-select to gen-
erate active low upper and lower byte chip-selects for a 16-bit memory block composed of two 8-bit de-
vices. Figure 13 shows a typical circuit.
Figure 13 Upper and Lower Byte Chip-Select Generation
1. There is no way to externally differentiate long word transfers from word transfers. Aligned
long word transfers are treated as two aligned word transfers. Misaligned long word trans-
fers are treated as two misaligned word transfers.
2. “X” indicates that the state of the signal has no effect upon operand alignment.
Table 20 Operand Alignment
Transfer Case1
SIZE
ADDR0
DATA[15:8]
DATA[7:0]
Byte to 8-Bit Port (Even/Odd)
X2
0/1
OP0
—
Byte to 16-Bit Port (Even)
1
0
OP0
—
Byte to 16-Bit Port (Odd)
1
—
OP0
Word to 8-Bit Port (Aligned/Misaligned)
0/1
OP0
—
Word to 16-Bit Port (Aligned)
0
OP0
OP1
Word to 16-Bit Port (Misaligned)
X
1
—
OP0
UPPER BYTE
CHIP SELECT
16 8/16-BIT DECODE
(DATA [15:8])
ADDR0
LOWER BYTE
CHIP SELECT
(DATA [7:0])
CHIP SELECT
ADDR0
SIZE
CHIP SELECT
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