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參數(shù)資料
| 型號(hào)： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 62/128頁(yè) |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MC68HC16V1
MOTOROLA
MC68HC16V1TS/D
39
Figure 11 RD and WR Generation
3.5.10 Data Transfer Acknowledge
External bus cycles must be terminated by DTACK. DTACK can be supplied either by SLIM chip-select
logic or by asserting the DTACK pin if it is configured for its primary function. Modules internal to the
MCU supply their own DTACK after completing a bus cycle. During a read cycle, DTACK signals the
MCU to terminate the bus cycle and latch data. During a write cycle, DTACK indicates that data has
been successfully stored and that the cycle can end. If the DTACK pin is asserted before SLIM chip-
select logic generates DTACK, the EBI terminates the bus cycle without waiting for the chip-select logic
to do so.
3.5.11 Data Transfer Mechanism
The MCU architecture supports byte or word operand transfers. The EBI can be configured to support
either 8 or 16-bit data bus operation on a per chip-select basis. Dynamic bus sizing by external devices
is not supported.
Each port (port referring to the width of the data path that an external device uses during a data transfer)
is assigned to particular bits of the data bus. A 16-bit port is assigned to data bus bits [15:0], and an 8-
bit port is assigned to data bus bits [15:8].
In multiplexed modes, address and data share the same bus. In the first part of the bus cycle the ad-
dress is driven on the address/data bus. At this time, an external device should use ALE to latch the
address. The address/data bus is then used for data transfer.
Operand bytes are designated as shown in Figure 12. OP0 is the most significant byte of a long-word
operand, and OP3 is the least significant byte. The two bytes of a word-length operand are OP0 (most
significant) and OP1. The single byte of a byte-length operand is OP0.
Figure 12 Operand Byte Order
3.5.12 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. Positioning of bytes is determined by the SIZE and ADDR0 outputs. SIZE indicates whether
a byte (SIZE = 1) or a word (SIZE = 0) remains to be transferred during the current bus cycle.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[17:1] in-
dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base.
Operand
Byte Order
31
24
23
16
15
8
7
0
Long Word
OP0
OP1
OP2
OP3
Word
OP0
OP1
Byte
OP0
16 R/W RD/WR SIGNALS
WR
R/W
DS
RD
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