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參數(shù)資料
| 型號： | MC16V1CPU20B1 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 59/128頁 |
| 文件大?。?/td> | 571K |
| 代理商： | MC16V1CPU20B1 |
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MOTOROLA
MC68HC16V1
36
MC68HC16V1TS/D
Convert the result of the formula above into hexadecimal and place the MSW in the SWP register and
the LSW in the RTP register.
These calculations give the real-time period ranges shown in Table 17.
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external de-
vices. The external bus has 18 address lines and 16 data lines.
The EBI operates as a bus master and allows the CPU to access external memory resources. The EBI
runs external bus cycles based on the programming of the chip-select base address and option regis-
ters, and the chip select pin options programmed in the port D pin assignment register.
The EBI supports byte, word, and long-word transfers. Ports are accessed through the use of asynchro-
nous cycles controlled by the data size (SIZE) and data transfer acknowledge (DTACK) pins.
External bus operation is synchronous to the clock output (CLKOUT) signal. The external bus speed is
programmable from two to 16 clock cycles (0 to 14 wait states) with optional external bus termination
using the DTACK signal. The bus speed is programmed on a per chip-select basis in the DTACK field
of each chip-select option register (CSOR).
At least one chip-select must be programmed to provide external bus cycle termination unless bus cy-
cles are to be terminated by the use of the DTACK function. Chip-selects used to access external mem-
ories or peripherals can be programmed for 8- or 16-bit, multiplexed or non-multiplexed accesses on a
per chip-select basis. Operation of the boot chip-select, CSB, can be overridden by the state of the
ADDR/DATA[8:7] pins during reset. Refer to 3.6.2 Default Configuration Override During Reset for
more information.
3.5.1 Transfer Size
At the beginning of a bus cycle, the SIZE signal is driven along with the function code signals. The SIZE
signal is only relevant for 16-bit port accesses and indicates the number of bytes remaining to be trans-
ferred during an operand cycle (refer to Table 18). It is valid while the address strobe (AS) is asserted.
1. The resolution of each range within a system frequency category is the range’s lower bound. For example, in
the first row of the 32.768 kHz column, the resolution is 61.0
s.
Table 17 Timer Period Ranges (Downcounters Chained)
RTDC
Clock Source
Time-Out Ranges for Typical Values of fref and fsys
1
32.768 kHz
4.194 MHz
16.777 MHz
20.972 MHz
fsys/2 or fref/2
61.0
s to 72.8 hrs
477 ns to 34.1 mins
119 ns to 8.53 mins
95.4 ns to 6.83 mins
fpre/16
977
s to 48.5 days
7.63
s to 9.10 hrs
1.91
s to 8102 s
1.53
s to 1.82 hrs
fpre/64
3.91 ms to 194 days
30.5
s to 36.4 hrs
7.63
s to 9.10 hrs
6.10
s to 7.28 hrs
fpre/256
15.6 ms to 2.13 yrs
122
s to 6.07 days
30.5
s to 36.4 hrs
24.4
s to 29.1 hrs
fpre/1024
62.5 ms to 8.51 yrs
488
s to 24.3 days 122 s to 6.07 days
97.7
s to 4.85 days
Table 18 SIZE Signal Encoding
SIZE
Transfer Size
1
Byte
0
Word
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