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19
MBM29LV008T-X/MBM29LV008B-X
DQ
3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
3
will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial Sector Erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ
3
may be
used to determine if the sector erase timer window is still open. If DQ
3
is high (“1”) the internally controlled erase
cycle has begun; attempts to write subsequent commands (except erase suspend command) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If DQ
3
is low (“0”),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ
3
prior to and following each subsequent Sector Erase command. If DQ
3
were high on the second status check, the command may not have been accepted.
See Table 7: Hardware Sequence Flags.
DQ
2
Toggle Bit II
This Toggle Bit II, along with DQ
6
, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ
2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ
2
to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ
2
bit.
DQ
6
is different from DQ
2
in that DQ
6
toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress.
For example, DQ
2
and DQ
6
can be used together to determine the erase-suspend-read mode. (DQ
2
toggles
while DQ
6
does not.) See also Table 7 and Figure 16.
Furthermore, DQ
2
can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ
2
toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29LV008T-X/008B-X provide a RY/BY open-drain output pin as a way to indicate to the host system
that the Embedded Algorithms are either in progress or completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If
the MBM29LV008T-X/008B-X are placed in an Erase Suspend mode, the RY/BY output will be high. Also, since
this is an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to V
CC
.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to Figure 12 and 13 for a detailed timing diagram.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.