參數(shù)資料
型號(hào)： MBM29LV008T-X
廠商： Fujitsu Limited
英文描述： CMOS 8M (1M ×8) Flash Memory(CMOS 8M (1M ×8)位3V單電源 閃速存儲(chǔ)器)
中文描述： 800萬(wàn)的CMOS（100萬(wàn)× 8）快閃記憶體（800萬(wàn)的CMOS（100萬(wàn)× 8）位3V的單電源閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 14/47頁(yè)
文件大?。?/td> 434K
代理商： MBM29LV008T-X
14
MBM29LV008T-X/MBM29LV008B-X
Notes:
1. Address bits A
15
to A
19
= X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
the WE pulse.
SA = Address of the sector to be erased. The combination of A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, and A
13
will uniquely
select any sector.
4. RD =Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.
5. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to read
mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase
Resume (30H) commands are valid only while the sector Erase operation is in progress. Moreover both Read/
Reset commands are functionally equivalent, resetting the device to the read mode.
Read/Reset Command
The read or reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Table 6 MBM29LV008T-X/B-X Command Definitions
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr.
Data
Addr.
Data Addr. Data Addr. Data
Addr.
Data Addr. Data
Read/Reset
1
XXXXH F0H
—
—
—
—
—
—
—
—
—
—
Read/Reset
3
5555H AAH 2AAAH 55H 5555H F0H
RA
RD
—
—
—
—
Autoselect
3
5555H AAH 2AAAH 55H 5555H 90H
—
—
—
—
—
—
Program
4
5555H AAH 2AAAH 55H 5555H A0H
PA
PD
—
—
—
—
Chip Erase
6
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase
6
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SA
30H
Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Addr (“H” or “L”). Data (30H)
相關(guān)PDF資料
PDF描述
MBM29LV008BA 8M (1M X 8) BIT
MBM29LV008BA-90PTR 8M (1M X 8) BIT
MBM29LV008TA-12 8M (1M X 8) BIT
MBM29LV008TA-12PTN 8M (1M X 8) BIT
MBM29LV008TA-12PTR 8M (1M X 8) BIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MBM29LV016B 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M x 8) BIT
MBM29LV016B-12 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M x 8) BIT
MBM29LV016B-12PTN 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M x 8) BIT
MBM29LV016B-12PTR 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M x 8) BIT
MBM29LV016B-80 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M x 8) BIT
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