參數(shù)資料
型號： MB91F267APMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁數(shù)： 40/53頁
文件大小： 0K
描述： IC MCU FLASH 128KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝： 1
系列： FR MB91265A
核心處理器： FR60Lite RISC
芯體尺寸： 32-位
速度： 33MHz
連通性： UART/USART
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 49
程序存儲器容量： 128KB（128K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 865-1092
48
8183F–AVR–06/12
ATtiny24A/44A/84A
Address
Labels Code
Comments
0x0000
rjmp
RESET
; Reset Handler
0x0001
rjmp
INT0
; IRQ0 Handler
0x0002
rjmp
PCINT0
; PCINT0 Handler
0x0003
rjmp
PCINT1
; PCINT1 Handler
0x0004
rjmp
WDT
; Watchdog Interrupt Handler
0x0005
rjmp
TIM1_CAPT
; Timer1 Capture Handler
0x0006
rjmp
TIM1_COMPA
; Timer1 Compare A Handler
0x0007
rjmp
TIM1_COMPB
; Timer1 Compare B Handler
0x0008
rjmp
TIM1_OVF
; Timer1 Overflow Handler
0x0009
rjmp
TIM0_COMPA
; Timer0 Compare A Handler
0x000A
rjmp
TIM0_COMPB
; Timer0 Compare B Handler
0x000B
rjmp
TIM0_OVF
; Timer0 Overflow Handler
0x000C
rjmp
ANA_COMP
; Analog Comparator Handler
0x000D
rjmp
ADC
; ADC Conversion Handler
0x000E
rjmp
EE_RDY
; EEPROM Ready Handler
0x000F
rjmp
USI_STR
; USI STart Handler
0x0010
rjmp
USI_OVF
; USI Overflow Handler
;
0x0011
RESET: ldi
r16, high(RAMEND); Main program start
0x0012
out
SPH,r16
; Set Stack Pointer to top of RAM
0x0013
ldi
r16, low(RAMEND)
0x0014
out
SPL,r16
0x0015
sei
; Enable interrupts
0x0016
<instr>
...
9.2
External Interrupts
External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as out-
puts. This feature provides a way of generating a software interrupt. Pin change 0 interrupts
PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1 interrupts PCI1 will trigger
if any enabled PCINT[11:8] pin toggles. The PCMSK0 and PCMSK1 Registers control which
pins contribute to the pin change interrupts. Pin change interrupts on PCINT[11:0] are detected
asynchronously, which means that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as
shown in “MCUCR – MCU Control Register” on page 50. When the INT0 interrupt is enabled
and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock,
9.2.1
Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source
can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in
all sleep modes except Idle).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB91F267APMC-GS 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers
MB91F267APMC-GSE1 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers
MB91F267N 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontroller
MB91F267NA 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers
MB91F267NAPMC-G 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Proprietary Microcontrollers
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