參數(shù)資料
型號(hào): MB91F267APMC-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 1/53頁
文件大小: 0K
描述: IC MCU FLASH 128KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91265A
核心處理器: FR60Lite RISC
芯體尺寸: 32-位
速度: 33MHz
連通性: UART/USART
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 49
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 865-1092
DS07-16702-4Ea
FUJITSU MICROELECTRONICS
DATA SHEET
“Check Sheet” is seen at the following support page
URL : http://edevice.fujitsu.com/micom/en-support/
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
Copyright2005-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2007.8
32-bit Microcontrollers
CMOS
FR60Lite MB91265A Series
MB91267A/267NA/F267A/F267NA/V265A
■ DESCRIPTION
The MB91265A series is a 32-bit RISC microcontroller designed by Fujitsu Microelectronics for embedded control
applications which require high-speed processing.
The CPU is used the FR family* and the compatibility of FR60Lite.
MB91267NA/F267NA loads the C-CAN (1 channel) .
* : FR is the abbreviation of FUJITSU RISC controller.
■ FEATURES
FR60Lite CPU
32-bit RISC, load/store architecture with a five-stage pipeline
Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
16-bit fixed length instructions (basic instructions)
Execution speed of instructions : 1 instruction per cycle
Memory-to-memory transfer, bit handling, barrel shift instructions, etc. : Instructions suitable for embedded
applications
Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
Register interlock function : Facilitates coding in assembler.
Built-in multiplier with instruction-level support
32-bit multiplication with sign : 5 cycles
16-bit multiplication with sign : 3 cycles
Interrupt (PC, PS save) : 6 cycles, 16 priority levels
Harvard architecture allowing program access and data access to be executed simultaneously
Instruction compatible with FR family
(Continued)
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