參數(shù)資料
型號(hào)： MB91F267APMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁(yè)數(shù)： 27/53頁(yè)
文件大小： 0K
描述： IC MCU FLASH 128KB FLASH 64LQFP
標(biāo)準(zhǔn)包裝： 1
系列： FR MB91265A
核心處理器： FR60Lite RISC
芯體尺寸： 32-位
速度： 33MHz
連通性： UART/USART
外圍設(shè)備： DMA，WDT
輸入/輸出數(shù)： 49
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 865-1092
36
8183F–AVR–06/12
ATtiny24A/44A/84A
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. See “Internal Voltage
Reference” on page 41 for details on the start-up time.
7.4.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. See “Watchdog Timer” on page 41 for details on how to configure the Watchdog Timer.
7.4.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk
I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. See the section “Digital Input Enable and Sleep Modes” on page 56 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See
7.5
Register Description
7.5.1
MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
Bit 7 – BODS: BOD Sleep
In order to disable BOD during sleep (see Table 7-1 on page 33) the BODS bit must be written to
logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,
both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be
set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is
set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for
the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
In devices where Sleeping BOD has not been implemented this bit is unused and will always
read zero.
Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
Bit
76543210
BODS
PUD
SE
SM1
SM0
BODSE
ISC01
ISC00
MCUCR
Read/Write
R/W
Initial Value
00000000
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