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參數(shù)資料
| 型號： | MB90F395HAPMT |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 66/72頁 |
| 文件大?。?/td> | 1734K |
| 代理商： | MB90F395HAPMT |
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69
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.10 Block Diagram of Dot Size Control Circuit
8.11.2 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
The dot size of each block is specified by bits 2 to 4 of the block
control register i.
Refer to Figure 8.11.4 (the structure of the block control register).
The block diagram of dot size control circuit is shown in Figure 8.11.10.
Fig. 8.11.11 Definition of Dot Sizes
Data slicer clock
HSYNC
OSC1
OC3 or OC4
Synchronous
circuit
Cycle ! 3
Pre-divide circuit
Clock cycle
= 1TC
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
Cycle ! 2
“0”
“1”
BCi4
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
1 dot
Scanning line ofF1(F2)
Scanning line ofF2(F1)
1/2H
1H
2H
3H
3TC
2TC
1TC
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