參數(shù)資料
型號： MB90F395HAPMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 53/72頁
文件大?。?/td> 1734K
代理商： MB90F395HAPMT
57
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit. The data clock stores cap-
tion data to the 16-bit shift register. When the 16-bit data has been
stored and the clock run-in determination circuit determines clock
run-in, the caption data latch completion flag is set. This flag is reset
at a falling of the vertical synchronous signal (Vsep).
Fig. 8.10.11 Data Clock Position Register
b7b6b5b4b3b2b1b0
Data clock position register (DPS) [Address 00E516]
Data Clock Position Register
01
RW
Fix this bit to “0.”
1Fix this bit to “1.”
0R W
10
0
B
After reset
Functions
Name
RW
3
Data clock position set
bits (DPS3 to DPS7)
1R W
4
to
7
0
2Fix this bit to “0.”
0R W
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