參數(shù)資料
型號： MB90F395HAPMT
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 63/72頁
文件大?。?/td> 1734K
代理商： MB90F395HAPMT
66
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), it starts to count the rising edge
(falling edge) of HSYNC signal from after fixed cycle of rising edge
(falling edge) of VSYNC signal. So interval from rising edge (falling
edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
The polarity of HSYNC and VSYNC signals can select with the I/O po-
larity control register (address 00D816).
Fig. 8.11.6 Supplement Explanation for Display Position
When bits 0 and 1 of the I/O polarity control register
(address 00D816) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.25 to 0.50 [
s]
( at f(XIN) = 8MHz)
Period of counting
HSYNC signal
(See note 2)
HSYNC
signal input
Not count
12345
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
8 machine cycles
or more
8 machine cycles
or more
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