參數(shù)資料
型號(hào)： MB90F395HAPMT
廠商： FUJITSU LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁(yè)數(shù)： 50/72頁(yè)
文件大小： 1734K
代理商： MB90F395HAPMT
54
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.6 Data Slice Line Specification Circuit
(1) Specification of data slice line
This circuit decides a line on which caption data is superimposed.
The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2
line for a period of 1 field), and both fields (F1 and F2) are sliced
their data. The caption position register (address 00E616) is used
for each setting (refer to Table 8.10.1).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position
register (at setting only 1 appropriate line). Figure 8.10.8 shows
the signals in the vertical blanking interval. Figure 8.10.9 shows
the structure of the caption position register.
(2) Specification of line to set slice voltage
The reference voltage for slicing (slice voltage) is generated for
the clock run-in pulse in the particular line (refer to Table 8.10.1).
The field to generate slice voltage is specified by bit 1 of data
slicer control register 1. The line to generate slice voltage 1 field is
specified by bits 6, 7 of the caption position register (refer to
Table 8.10.1).
Fig. 8.10.8 Signals in Vertical Blanking Interval
(3) Field determination
The field determination flag can be read out by bit 3 of data slicer
control register 2. This flag charge at the falling edge of Vsep.
Video signal
Vertical blanking interval
Composite
video signal
Count value to be set in the caption position register (“0F 16” in this case)
Hsep
Vsep
Hsep
Magnified
drawing
Clock run-in
Start bit + 16-bit data
Start bit
Window for
deteminating
clock-run-in
Composite video
signal
Line 21
1 appropriate line is set by
the caption position register
(when setting line 19)
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