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M88 FAMILY
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable and can have the following
functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 8).
5. Address inputs. For example, PA0-3 could be used for A[0:3] when using an 80C51XA
in burst mode.
6. As the data bus inputs D[0:7] for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-3 can only output CMOS signals with an option for high slew rate. However,
PA4-7 can be configured as CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
I/O
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 8).
Note: PB0-3 can only output CMOS signals with an option for high slew rate. However,
PB4-7 can be configured as CMOS or Open Drain Outputs.
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input2 for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC2
18
I/O
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC2) output.
3. Input to the PLDs.
4. VSTBY — SRAM stand-by voltage input for SRAM battery backup.
This pin can be configured as a CMOS or Open Drain output.
PC3
17
I/O
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output2 for the JTAG interface.
5. Ready/Busy output for in-system parallel programming.
This pin can be configured as a CMOS or Open Drain output.
PC4
14
I/O
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC4) output.
3. Input to the PLDs.
4. TERR output2 for the JTAG interface.
5. VBATON — battery backup indicator output. Goes high when power is being drawn from
an external battery.
This pin can be configured as a CMOS or Open Drain output.
Pin Name
Pin1
Type
Description