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參數(shù)資料
| 型號： | M8803F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 49/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8803F3Y-90K1T |
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M88 FAMILY
Table 39. Operating Range
Table 40. Recommended Operating Condi tions
Range
Temperature
VCC
VCC Tolerance
–90
–15
Commercial
0
° Cto +70°C+ 5 V
± 10%
Industrial
–40
° Cto +85°C+ 5 V
± 10%
Commercial
0
° C to +70°C
+ 3 V
+20/–10%
Industrial
–40
° Cto +85°C
+ 3 V
+20/–10%
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
M88x3FxY
4.5
5
5.5
V
VCC
Supply Voltage
M88x3FxW
2.7
3
3.6
V
power-up. While the reset input is active, the PLD
is active and the outputs are determined by the
PSDabel equations. The chip status during reset
and Power Down Mode is shown in Table 36. The
reset input will not abort any active programming
or erase cycles in the main Flash or Boot block.
Programming In-Circuit using the JTAG
Interface
The
JTAG
interface
on
the
M88x3Fxx
FLASH+PSD can be enabled on Port C (see Table
37). All memory (Flash and EEPROM), PLD logic,
and PSD configuration bits may be programmed
through the JTAG interface. A blank part can be
mounted
on
a
printed
circuit
board
and
programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up program and erase operations.
By default, on a blank PSD, four pins on Port C are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
See Application Note AN1153 for more details on
JTAG In-System-Programming.
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different
conditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
serial command from an external JTAG controller
device (such as FlashLink or Automated Test
Equipment). When the enabling command is
received, TDO becomes an output and the JTAG
channel is fully functional inside the PSD. The
same command that enables the JTAG channel
may optionally enable the two additional JTAG
pins, TSTAT and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discussion, the logic
label JTAG_ON will be used. When JTAG_ON is
true, the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft_enabled
+
/* An NVM configuration bit inside the
PSD
is
set
by
the
designer
in
the
PSDsoft
Configuration
utility.
This
dedicates
the
pins
for
JTAG
at
all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled
+
/* The microcontroller can set a bit at
run-time
by
writing
to
the
PSD
register,
JTAG
Enable.
This
register
is
located
at
address
CSIOP
+ offset
C7h.
Setting
the
JTAG_ENABLE
bit
in
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset
or
the
microcontroller.
See
Table 38 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins.
This
PT
has
the
reserved
name
JTAGSEL.
Once
defined
as
a
node
in
PSDabel,
the
designer
can
write
an
equation
for
JTAGSEL.
This
method
is
used
when
the
Port
C
JTAG
pins
are
multiplexed with other I/O signals. It
is
recommended
to
logically
tie
the
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 for
details. */
The M88x3Fxx FLASH+PSD supports JTAG In-
System-Configuration (ISC) commands, but not
Boundary Scan. A definition of these JTAG-ISC
commands and sequences are defined in a
supplemental document available from ST. ST’s
PSDsoft software tool and FlashLink JTAG
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