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參數(shù)資料
| 型號(hào)： | M8803F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 42/85頁 |
| 文件大小： | 601K |
| 代理商： | M8803F3Y-90K1T |
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M88 FAMILY
Figu re 32. Port D External Chip Selects
PLD
INPUT
BUS
POLARITY
BIT
PD2 PIN
PT2
ECS2
DIRECTION
REGISTER
POLARITY
BIT
PD1 PIN
PT1
ECS1
ENABLE (.OE)
DIRECTION
REGISTER
POLARITY
BIT
PD0 PIN
PT0
ECS0
ENABLE (.OE)
DIRECTION
REGISTER
CPLD
AND
ARRAY
AI02890
Power Management
All
M88x3Fxx
FLASH+PSD
devices
offer
configurable power saving options. These options
may be used individually or in combinations, as
follows:
t All memory types in a PSD (Flash, EEPROM,
and SRAM) are built with Power Management
technology. In addition to using special silicon
design
methodology,
Power
Management
technology puts the memories into standby mode
when address/data inputs are not changing (zero
DC current). As soon as a transition occurs on an
input, the affected memory “wakes up”, changes
and latches its outputs, then goes back to standby.
The designer does not have to do anything special
to achieve memory standby mode when no inputs
are changing—it happens automatically. When
using Power Management family devices, the PLD
sections can also achieve standby mode when its
inputs are not changing.
t Like the Power Management feature, the
Automatic Power Down (APD) logic allows the
PSD to reduce to standby current automatically.
The APD can also block MCU address/data
signals from reaching the memories and PLDs.
This feature is available on all the devices of the
M88x3Fxx FLASH+PSD family. The APD unit is
described in more detail in the section entitled
“Automatic Power Down (APD) Unit and Power
Down Mode”, on page 48.
Built in logic will monitor the address strobe of the
MCU for activity. If there is no activity for a certain
time period (MCU is asleep), the APD logic
initiates Power Down Mode (if enabled). Once in
Power Down Mode, all address/data signals are
blocked from reaching PSD memories and PLDs,
and the memories are deselected internally. This
allows the memories and PLDs to remain in
standby mode even if the address/data lines are
changing state externally (noise, other devices on
the MCU bus, etc.). Keep in mind that any
unblocked PLD input signals that are changing
Table 31. Power Down Mode’s Effect on Ports
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
Address Out
Undefined
Data Port
Three-State
Peripheral I/O
Three-State
相關(guān)PDF資料 |
PDF描述 |
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| M8813F3Y-90K1T | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
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| M906-01-125.0000LF | 125 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01-187.5000LF | 187.5 MHz, OTHER CLOCK GENERATOR, CQCC36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M8805/100-007 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-007 |
| M8805/100-009 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-009 |
| M8805/100-010 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-010 |
| M8805/100-015 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-015 |
| M8805/100-016 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-016 |
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