參數(shù)資料
型號(hào): M8803F3Y-90K1T
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝: PLASTIC, LCC-52
文件頁(yè)數(shù): 45/85頁(yè)
文件大小: 601K
代理商: M8803F3Y-90K1T
5/85
M88 FAMILY
s
Optional 64 byte One Time Programmable
(OTP) memory (on the M8813F1x) that can be
used for product configuration and calibration.
s
CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (IMCs). The CPLD may be
used to implement efficiently a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
s
Decode PLD (DPLD) that decodes address for
selection of internal memory blocks. The DPLD
can also be used to generate external chip
selects.
s
27 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os
– 16 of the I/O ports may be configured as
open-drain outputs.
s
Stand-by current as low as 50
A for 5 V
devices, 25
A for 3 V devices.
s
Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
s
Internal page register that can be used to
expand the microcontroller address space by a
factor of 256.
s
Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the M88x3Fxx FLASH+PSD into
Power Down Mode.
GENERAL INFORMATION
The M88x3Fxx FLASH+PSD architecture allows
In-System Programming of all Memory, PLD Logic
and Device Configuration. The embedded Input
and
Output
Macrocells
enable
efficient
implementation of user defined logic functions that
require both software and hardware interaction.
The devices eliminate the need for discrete ‘glue’
logic, and allow the development of entire systems
using only a few highly integrated devices.
M88X3FXX FLASH+PSD FAMILY
All M88x3Fxx FLASH+PSD devices provide the
base features: 1 Mbit main Flash Memory, JTAG
port, CPLD, DPLD, power management, and
twenty-seven I/O pins. Some of the members of
the M88x3Fxx FLASH+PSD family add to this set
of basic features:
s
M8813Fxx adds 16 Kbit (2K x 8) SRAM to the
base feature set.
s
M8813F1x adds 256 Kbit (32K x 8) EEPROM to
the base feature set. It also adds 64 bytes of
OTP memory for any use (product serial
number, calibration constants, etc.). Once
written, the OTP memory can never be altered.
s
M88x3F2x adds a secondary 256 Kbit (32K x 8)
Flash memory to the base feature set.
These
independent
memories
can
operate
concurrently with each other and with the main
Flash memory.
Table 2 summarizes all the devices in the
M88x3Fxx FLASH+PSD family.
M88X3FXX FLASH+PSD ARCHITECTURAL
OVERVIEW
M88x3Fxx FLASH+PSD devices contain several
major functional blocks. Figure 3 shows the
architecture of the M88x3Fxx FLASH+PSD device
family. The functions of each block are described
briefly in the following sections. Many of the blocks
perform
multiple
functions
and
are
user
configurable.
Memory
Each of the memories is briefly discussed in the
following paragraphs. A more detailed discussion
can be found in the section entitled “M88 Family
Functional Blocks”, on page 12.
The 1 Mbit (128K x 8) Flash memory is the main
memory of the M88x3Fxx FLASH+PSD. It is
divided into eight equally-sized blocks that are
individually selectable.
The optional 256 Kbit (32K x 8) EEPROM or Flash
memory is divided into four equally-sized blocks.
Each block is individually selectable.
The optional 16 Kbit (2K x 8) SRAM is intended for
use as a scratch-pad memory or as an extension
to the microcontroller SRAM. If an external battery
is connected to the M88x3Fxx FLASH+PSD’s
VSTBY pin, data will be retained in the event of a
power failure.
Each block of memory can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
相關(guān)PDF資料
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