M88 FAMILY
34/85
Figu re 20. An Example of a Typical 8-bit Multiplexed Bus Interface
MICRO -
CONTROLLER
WR
RD
BHE
ALE
RESET
AD [ 7:0]
A[ 15:8]
A[ 7:0]
ADIO
PORT
A
PORT
B
PORT
C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
M88x3Fxx
AI02878
Table 21. 80C251 Configurations
Configuration
80C251 Read/Write Pins
Connecting to M88x3Fxx
FLASH+PSD Pins
Page Mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A[7:0] multiplex with
D[7:0}
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A[7:0] multiplex with D[7:0}
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A[15:8] multiplex with D[7:0}
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A[15:8] multiplex with D[7:0}
by the MCU via the IMC buffer. See the section
entitled “I/O Ports”, on page 39.
IMCs can use the address strobe to latch address
bits higher than A15. Any latched addresses are
routed to the PLDs as inputs.
IMCs are particularly useful with handshaking
communication
applications
where
two
processors pass data back and forth through a
common mailbox. Figure 19 shows a typical
configuration where the Master MCU writes to the
Port A Data Out Register. This, in turn, can be
read by the Slave MCU via the activation of the
“Slave-Read” output enable product term.
or to pass incoming Port signals prior to driving
them onto the PLD input bus. The outputs of the
IMCs can be read by the microcontroller through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND array or the
MCU address strobe (ALE/AS). Each product term
output is used to latch or clock four IMCs. Port
inputs 3-0 can be controlled by one product term
and 7-4 by another.
Configurations for the IMCs are specified by
equations written in PSDabel (see Application
Note AN1171). Outputs of the IMCs can be read