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參數(shù)資料
| 型號： | M8803F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 27/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8803F3Y-90K1T |
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M88 FAMILY
the section entitled “I/O Ports”, on page 39). The
flip-flops in each of the 16 OMCs can be loaded
from the data bus by a microcontroller. Loading
the OMCs with data from the MCU takes priority
over internal functions. As such, the preset, clear,
and clock inputs to the flip-flop can be overridden
by the MCU. The ability to load the flip-flops and
read them back is useful in such applications as
loadable counters and shift registers, mailboxes,
and handshaking protocols.
Data can be loaded to the OMCs on the trailing
edge of the WR signal (edge loading) or during the
time that the WR signal is active (level loading).
The method of loading is specified in PSDsoft
Configuration.
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight OMCs. The Mask Registers can be
used to block the loading of data to individual
OMCs. The default value for the Mask Registers is
00h, which allows loading of the OMCs. When a
given bit in a Mask Register is set to a ‘1’, the MCU
will be blocked from writing to the associated
OMC. For example, suppose McellAB0-3 are
being used for a state machine. You would not
want a MCU write to McellAB to overwrite the state
machine registers. Therefore, you would want to
load the Mask Register for McellAB (Mask
Macrocell AB) with the value 0Fh.
The Output Enable of the OMC
The OMC can be connected to an I/O port pin as
a PLD output. The output enable of each Port pin
driver is controlled by a single product term from
the AND array, ORed with the Direction Register
output. The pin is enabled upon power up if no
output enable equation is defined and if the pin is
declared as a PLD output in PSDsoft.
If the OMC output is declared as an internal node
and not as a Port pin output in the PSDabel file,
then the Port pin can be used for other I/O
functions. The internal node feedback can be
routed as an input to the AND array.
Inpu t Macrocells (IMCs)
The CPLD has 24 IMCs, one for each pin on Ports
A, B, and C. The architecture of the IMC is shown
in
Figure
18.
The
IMCs
are
individually
configurable, and can be used as a latch, register,
Table 19. Microcontrollers and their Control Signals
Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PC7, PD0, PA3-0) can be configured for other I/O func-
tions.
2. ALE/AS input is optional for microcontrollers with a non-multiplexed bus
MCU
Data Bus
Wid th
CNTL0
CNTL1
CNTL2
PC7
PD02
ADIO0
PA3-PA0
PA7-PA3
8031
8
WR
RD
PSEN
(Note 1) ALE
A0
(Note 1)
80C51XA
8
WR
RD
PSEN
(Note 1) ALE
A4
A3-A0
(Note 1)
80C251
8
WR
PSEN
(Note 1) (Note 1) ALE
A0
(Note 1)
80C251
8
WR
RD
PSEN
(Note 1) ALE
A0
(Note 1)
80198
8
WR
RD
(Note 1) (Note 1) ALE
A0
(Note 1)
68HC11
8
R/W
E
(Note 1) (Note 1) AS
A0
(Note 1)
68HC912
8
R/W
E
(Note 1) DBE
AS
A0
(Note 1)
Z80
8
WR
RD
(Note 1) (Note 1) (Note 1) A0
D3-D0
D7-D4
NEURON 3150 CHIP
8
R/W
E
(Note 1) (Note 1) (Note 1) A0
D3-D0
D7-D4
Z8
8
R/W
DS
(Note 1) (Note 1) AS
A0
(Note 1)
68330
8
R/W
DS
(Note 1) (Note 1) AS
A0
(Note 1)
M37702M2
8
R/W
E
(Note 1) (Note 1) ALE
A0
D3-D0
D7-D4
Table 20. Eight-Bit Data Bus
BHE
A0
D7-D0
X
0
Even Byte
X
1
Odd Byte
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