參數(shù)資料
型號: M8803F3Y-90K1T
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 67/85頁
文件大?。?/td> 601K
代理商: M8803F3Y-90K1T
7/85
M88 FAMILY
JTAG Port
In-System
Programming
can
be
performed
through the JTAG pins on Port C. This serial
interface allows complete programming of the
entire M88x3Fxx FLASH+PSD device. A blank
device can be completely programmed. The JTAG
signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on Port C.
Table
5
indicates
the
JTAG
signals
pin
assignments.
Four-pin
JTAG
is
also
fully
supported.
In-System Programming
Using the JTAG signals on Port C, the entire
M88x3Fxx
FLASH+PSD
device
can
be
programmed or erased without the use of the
microcontroller. The main Flash memory can also
be programmed in-system by the microcontroller
executing the programming algorithms out of the
optional EEPROM, Flash Boot memory, or SRAM.
The optional EEPROM or Flash Boot memory can
be programmed the same way by executing out of
the main Flash memory. The PLD logic or other
M88x3Fxx FLASH+PSD configuration can be
programmed through the JTAG port or a device
programmer.
Table
6
indicates
which
programming methods can program different
functional blocks of the M88x3Fxx FLASH+PSD.
Power Management Unit
The Power Management Unit (PMU) in the
M88x3Fxx FLASH+PSD gives the user control of
the power consumption on selected functional
blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD)
that
will
turn
off
device
functions
due
to
microcontroller inactivity. The APD unit has a
Power Down Mode that helps reduce power
consumption.
The M88x3Fxx FLASH+PSD also has some bits
that are configured at run-time by the MCU to
reduce power consumption of the CPLD. The
turbo bit in the PMMR0 register can be turned off
and the CPLD will latch its outputs and go to sleep
until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set
by the MCU to block signals from entering the
CPLD to reduce power consumption. See the
section entitled “Power Management”, on page
47.
Figu re 4. PSDsoft Development Tools
PSD Configuration
PSD Fitter
PSD Simulator
PSD Programmer
*.OBJ FILE
PLD DESCRIPTION
CONFIGURE MCU BUS
INTERFACE AND OTHER
PSD ATTRIBUTES
LOGIC SYNTHESIS
AND FITTING
PSDsilos III
DEVICE SIMULATION
(OPTIONAL)
PSDPro, or
FlashLink (JTAG)
ADDRESS TRANSLATION
AND MEMORY MAPPING
PSDabel
MODIFY ABEL TEMPLATE FILE
OR GENERATE NEW FILE
PSD TOOLS
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
USER’S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ AND *.SVF
FILES AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
FIRMWARE
HEX OR S-RECORD
FORMAT
AI02862
相關(guān)PDF資料
PDF描述
M8813F3Y-90K1T 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
M906-01-125.0000LF 125 MHz, OTHER CLOCK GENERATOR, CQCC36
M906-01-125.0000LF 125 MHz, OTHER CLOCK GENERATOR, CQCC36
M906-01-187.5000LF 187.5 MHz, OTHER CLOCK GENERATOR, CQCC36
M906-01I156.2500 156.25 MHz, OTHER CLOCK GENERATOR, CQCC36
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