MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
5-31
Table 5-1.
DTACK
,
BERR
, and
HALT
Assertion Results
Case
No.
Control
Signal
Asserted on
Rising Edge
of State
MC68000/MC68HC000/001
EC000/MC68008 Results
MC68010 Results
N
N+2
1
DTACK
BERR
HALT
A
NA
NA
S
NA
X
Normal cycle terminate and continue.
Normal cycle terminate and continue.
2
DTACK
BERR
HALT
A
NA
A/S
S
NA
S
Normal cycle terminate and halt.
Continue when
HALT
negated.
Normal cycle terminate and halt.
Continue when
HALT
negated.
3
DTACK
BERR
HALT
X
A
NA
X
S
NA
Terminate and take bus error trap.
Terminate and take bus error trap.
4
DTACK
BERR
HALT
A
NA
NA
S
A
NA
Normal cycle terminate and continue.
Terminate and take bus error trap.
5
DTACK
BERR
HALT
X
A
A/S
X
S
S
Terminate and retry when
HALT
removed.
Terminate and retry when
HALT
removed.
6
DTACK
BERR
HALT
A
NA
NA
S
A
A
Normal cycle terminate and continue.
Terminate and retry when
HALT
removed.
LEGEND:
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
NA
— Signal not asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
NOTE: All operations are subject to relevant setup and hold times.
The negation of
BERR
and
HALT
under several conditions is shown in Table 5-6. (
DTACK
is assumed to be negated normally in all cases; for reliable operation, both
DTACK
and
BERR
should be negated when address strobe is negated).
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts
BERR
after timeout (case 3).
EXAMPLE B:
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
1. Delay
DTACK
until the data is verified. If data is invalid, return
BERR
and
HALT
simultaneously to retry the error cycle (case 5).
2. Delay
DTACK
until the data is verified. If data is invalid, return
BERR
at the same
time as
DTACK
(case 3).
3. For an MC68010, return
DTACK
before data verification. If data is invalid, assert
BERR
and
HALT
to retry the error cycle (case 6).