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參數(shù)資料
| 型號(hào)： | M68HC001 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-/32-Bit Microprocessor(16/32位微處理器) |
| 中文描述： | 16/32位微處理器（16/32位微處理器） |
| 文件頁(yè)數(shù)： | 41/184頁(yè) |
| 文件大?。?/td> | 1006K |
| 代理商： | M68HC001 |
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MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
4-3
A bus cycle consists of eight states. The various signals are asserted during specific
states of a read cycle, as follows:
STATE 0
The read cycle starts in state 0 (S0). The processor places valid function
codes on FC0–FC2 and drives R/
W
high to identify a read cycle.
STATE 1
Entering state 1 (S1), the processor drives a valid address on the address
bus.
STATE 2
On the rising edge of state 2 (S2), the processor asserts
AS
and
LDS
,
or
DS
.
STATE 3
During state 3 (S3), no bus signals are altered.
STATE 4
During state 4 (S4), the processor waits for a cycle termination signal
(
DTACK
or
BERR
) or
VPA
, an M6800 peripheral signal. When
VPA
is
asserted during S4, the cycle becomes a peripheral cycle (refer to
Appendix B M6800 Peripheral Interface
). If neither termination signal is
asserted before the falling edge at the end of S4, the processor inserts wait
states (full clock cycles) until either
DTACK
or
BERR
is asserted.
STATE 5
During state 5 (S5), no bus signals are altered.
STATE 6
During state 6 (S6), data from the device is driven onto the data bus.
STATE 7
On the falling edge of the clock entering state 7 (S7), the processor latches
data from the addressed device and negates
AS
and
LDS
, or
DS
. At
the rising edge of S7, the processor places the address bus in the high-
impedance state. The device negates
DTACK
or
BERR
at this time.
NOTE
During an active bus cycle,
VPA
and
BERR
are sampled on
every falling edge of the clock beginning with S4, and data is
latched on the falling edge of S6 during a read cycle. The bus
cycle terminates in S7, except when
BERR
is asserted in the
absence of
DTACK
. In that case, the bus cycle terminates one
clock cycle later in S9.
4.1.2 Write Cycle
During a write cycle, the processor sends bytes of data to the memory or peripheral
device. Figures 4-3 and 4-4 illustrate the write-cycle operation
The 8-bit operation performs two write cycles for a word write operation, issuing the data
strobe signal during each cycle. The address bus includes the A0 bit to select the desired
byte.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68EC000 | 16/32 Bit Microprocesso(16/32位微處理器) |
| M68HC16 | 16-Bit Microcontroller(16位微控制器) |
| MAC08BT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
| MAC08MT1 | SENSITIVE GATE TRIACS |
| MAC08DT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M68HC05 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| M68HC05_13 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC05 Microcontrollers |
| M68HC05EVS | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Motorola M68HC05 Family Evaluation System |
| M68HC05M68H | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Microcontroller Unit |
| M68HC08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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