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參數(shù)資料
| 型號(hào)： | M68HC000 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-/32-Bit Microprocessor(16/32位微處理器) |
| 中文描述： | 16/32位微處理器（16/32位微處理器） |
| 文件頁(yè)數(shù)： | 55/184頁(yè) |
| 文件大?。?/td> | 1006K |
| 代理商： | M68HC000 |
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MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
5-9
STATE 12
The write portion of the cycle starts in S12. The valid function codes on
FC2–FC0, the address bus lines,
AS
, and R/
W
remain unaltered.
STATE 13
During S13, no bus signals are altered.
STATE 14
On the rising edge of S14, the processor drives R/
W
low.
STATE 15
During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
STATE 16
At the rising edge of S16, the processor asserts
UDS
or
LDS
. The
processor waits for
DTACK
or
BERR
or
VPA
, an M6800 peripheral signal.
When
VPA
is asserted during S16, the cycle becomes a peripheral cycle
(refer to
Appendix B M6800 Peripheral Interface
). If neither termination
signal is asserted before the falling edge at the close of S16, the processor
inserts wait states (full clock cycles) until either
DTACK
or
BERR
is asserted.
STATE 17
During S17, no bus signals are altered.
STATE 18
During S18, no bus signals are altered.
STATE 19
On the falling edge of the clock entering S19, the processor negates
AS
,
UDS
, and
LDS
. As the clock rises at the end of S19, the processor
places the address and data buses in the high-impedance state, and drives
R/
W
high. The device negates
DTACK
or
BERR
at this time.
5.1.4 CPU Space Cycle
A CPU space cycle, indicated when the function codes are all high, is a special processor
cycle. Bits A16–A19 of the address bus identify eight types of CPU space cycles. Only the
interrupt acknowledge cycle, in which A16–A19 are high, applies to all the
microprocessors described in this manual. The MC68010 defines an additional type of
CPU space cycle, the breakpoint acknowledge cycle, in which A16–A19 are all low. Other
configurations of A16–A19 are reserved by Motorola to define other types of CPU cycles
used in other M68000 Family microprocessors. Figure 5-10 shows the encoding of CPU
space addresses.
BREAKPOINT
ACKNOWLEDGE
(MC68010 only)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
1
1
1
1
1
INTERRUPT
ACKNOWLEDGE
FUNCTION
CODE
2
0
31
31
23
19
16
0
CPU SPACE
TYPE FIELD
LEVEL
1
3
1 0
ADDRESS BUS
Figure 5-10. CPU Space Address Encoding
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC001 | 16-/32-Bit Microprocessor(16/32位微處理器) |
| M68EC000 | 16/32 Bit Microprocesso(16/32位微處理器) |
| M68HC16 | 16-Bit Microcontroller(16位微控制器) |
| MAC08BT1 | TRIAC 0.8 AMPERE RMS 200 thru 600 Volts |
| MAC08MT1 | SENSITIVE GATE TRIACS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M68HC05 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| M68HC05_13 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:M68HC05 Microcontrollers |
| M68HC05EVS | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Motorola M68HC05 Family Evaluation System |
| M68HC05M68H | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:HCMOS Microcontroller Unit |
| M68HC08 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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