參數(shù)資料
型號(hào): M68HC000
廠商: Motorola, Inc.
英文描述: 16-/32-Bit Microprocessor(16/32位微處理器)
中文描述: 16/32位微處理器(16/32位微處理器)
文件頁(yè)數(shù): 105/184頁(yè)
文件大?。?/td> 1006K
代理商: M68HC000
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)當(dāng)前第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)
6-20
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
6.4 RETURN FROM EXCEPTION (MC68010)
In addition to returning from any exception handler routine on the MC68010, the RTE
instruction resumes the execution of a suspended instruction by returning to the normal
processing state after restoring all of the temporary register and control information stored
during a bus error. For the RTE instruction to execute properly, the stack must contain
valid and accessible data. The RTE instruction checks for data validity in two ways. First,
the format/offset word is checked for a valid stack format code. Second, if the format code
indicates the long stack format, the validity of the long stack data is checked as it is loaded
into the processor. In addition, the data is checked for accessibility when the processor
starts reading the long data. Because of these checks, the RTE instruction executes as
follows:
1. Determine the stack format. This step is the same for any stack format and consists
of reading the status register, program counter, and format/offset word. If the format
code indicates a short stack format, execution continues at the new program counter
address. If the format code is not an MC68010-defined stack format code, exception
processing starts for a format error.
2. Determine data validity. For a long-stack format, the MC68010 begins to read the
remaining stack data, checking for validity of the data. The only word checked for
validity is the first of the 16 internal information words (SP + 26) shown in Figure 5-8.
This word contains a processor version number (in bits 10–13) and proprietary
internal information that must match the version number of the MC68010 attempting
to read the data. This validity check is used to ensure that the data is properly
interpreted by the RTE instruction. If the version number is incorrect for this
processor, the RTE instruction is aborted and exception processing begins for a
format error exception. Since the stack pointer is not updated until the RTE
instruction has successfully read all the stack data, a format error occurring at this
point does not stack new data over the previous bus error stack information.
3. Determine data accessibility. If the long-stack data is valid, the MC68010 performs a
read from the last word (SP + 56) of the long stack to determine data accessibility. If
this read is terminated normally, the processor assumes that the remaining words on
the stack frame are also accessible. If a bus error is signaled before or during this
read, a bus error exception is taken. After this read, the processor must be able to
load the remaining data without receiving a bus error; therefore, if a bus error occurs
on any of the remaining stack reads, the error becomes a double bus fault, and the
MC68010 enters the halted state.
相關(guān)PDF資料
PDF描述
M68HC001 16-/32-Bit Microprocessor(16/32位微處理器)
M68EC000 16/32 Bit Microprocesso(16/32位微處理器)
M68HC16 16-Bit Microcontroller(16位微控制器)
MAC08BT1 TRIAC 0.8 AMPERE RMS 200 thru 600 Volts
MAC08MT1 SENSITIVE GATE TRIACS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M68HC05 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers
M68HC05_13 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:M68HC05 Microcontrollers
M68HC05EVS 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Motorola M68HC05 Family Evaluation System
M68HC05M68H 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:HCMOS Microcontroller Unit
M68HC08 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers