7-2
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
Table 7-1. Effective Address Calculation Times
Addressing Mode
Byte
Word
Long
Dn
An
Register
Data Register Direct
Address Register Direct
0
(0/0)
0
(0/0)
0
(0/0)
0
(0/0)
0
(0/0)
0
(0/0)
(An)
(An)+
Memory
Address Register Indirect
Address Register Indirect with Postincrement
4
(1/0)
4
(1/0)
8
(2/0)
8
(2/0)
16
(4/0)
16
(4/0)
–(An)
(d16, An)
(d8, An, Xn)*
(xxx).W
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
6
(1/0)
12
(3/0)
10
(2/0)
16
(4/0)
18
(4/0)
24
(6/0)
Address Register Indirect with Index
Absolute Short
14
(3/0)
12
(3/0)
18
(4/0)
16
(4/0)
26
(6/0)
24
(6/0)
(xxx).L
(d16, PC)
(d8, PC, Xn)*
#<data>
Absolute Long
Program Counter Indirect with Displacement
20
(5/0)
12
(3/0)
24
(6/0)
16
(3/0)
32
(8/0)
24
(6/0)
Program Counter Indirect with Index
Immediate
14
(3/0)
8
(2/0)
18
(4/0)
8
(2/0)
26
(6/0)
16
(4/0)
*The size of the index register (Xn) does not affect execution time.
7.2 MOVE INSTRUCTION EXECUTION TIMES
Tables 7-2, 7-3, and 7-4 list the numbers of clock periods for the move instructions. The
totals include instruction fetch, operand reads, and operand writes. The total number of
clock periods, the number of read cycles, and the number of write cycles are shown in the
previously described format.
Table 7-2. Move Byte Instruction Execution Times
Destination
Source
Dn
An
(An)
(An)+
–(An)
(d16, An)
20
(4/1)
20
(4/1)
24
(5/1)
(d8, An, Xn)*
22
(4/1)
22
(4/1)
26
(5/1)
(xxx).W
(xxx).L
Dn
An
(An)
8
(2/0)
8
(2/0)
12
(3/0)
8
(2/0)
8
(2/0)
12
(3/0)
12
(2/1)
12
(2/1)
16
(3/1)
12
(2/1)
12
(2/1)
16
(3/1)
12
(2/1)
12
(2/1)
16
(3/1)
20
(4/1)
20
(4/1)
24
(5/1)
28
(6/1)
28
(6/1)
32
(7/1)
(An)+
–(An)
(d16, An)
(d8, An, Xn)*
(xxx).W
(xxx).L
12
(3/0)
14
(3/0)
20
(5/0)
12
(3/0)
14
(3/0)
20
(5/0)
16
(3/1)
18
(3/1)
24
(5/1)
16
(3/1)
18
(3/1)
24
(5/1)
16
(3/1)
18
(3/1)
24
(5/1)
24
(5/1)
26
(5/1)
32
(7/1)
26
(5/1)
28
(5/1)
34
(7/1)
24
(5/1)
26
(5/1)
32
(7/1)
32
(7/1)
34
(7/1)
40
(9/1)
22
(5/0)
20
(5/0)
28
(7/0)
22
(5/0)
20
(5/0)
28
(7/0)
26
(5/1)
24
(5/1)
32
(7/1)
26
(5/1)
24
(5/1)
32
(7/1)
26
(5/1)
24
(5/1)
32
(7/1)
34
(7/1)
32
(7/1)
40
(9/1)
36
(7/1)
34
(7/1)
42
(9/1)
34
(7/1)
32
(7/1)
40
(9/1)
42
(9/1)
40
(9/1)
48
(11/1)
(d16, PC)
(d8, PC, Xn)*
#<data>
20
(5/0)
22
(5/0)
16
(4/0)
20
(5/0)
22
(5/0)
16
(4/0)
24
(5/1)
26
(5/1)
20
(4/1)
24
(5/1)
26
(5/1)
20
(4/1)
24
(5/1)
26
(5/1)
20
(4/1)
32
(7/1)
34
(7/1)
28
(6/1)
34
(7/1)
36
(7/1)
30
(6/1)
32
(7/1)
34
(7/1)
28
(6/1)
40
(9/1)
42
(9/1)
36
(8/1)
*The size of the index register (Xn) does not affect execution time.