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| 型號(hào)： | M68HC000 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-/32-Bit Microprocessor(16/32位微處理器) |
| 中文描述： | 16/32位微處理器（16/32位微處理器） |
| 文件頁(yè)數(shù)： | 152/184頁(yè) |
| 文件大?。?/td> | 1006K |
| 代理商： | M68HC000 |
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10-12
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
Num
Characteristic
8 MHz*
10 MHz*
12.5 MHz*
16.67 MHz
12F
16 MHz
20 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
47
5
Asynchronous Input Setup
Time
10
—
10
—
10
—
10
—
5
—
5
—
ns
48
2
,
3
BERR
Asserted to
DTACK
Asserted
48
2,3,5
DTACK
Asserted to
BERR
Asserted (MC68010 Only)
49
9
AS, DS,
Negated to E Low
20
—
20
—
20
—
10
—
10
—
10
—
ns
—
80
—
55
—
35
—
—
—
—
—
—
ns
-70
70
-55
55
-45
45
-35
35
-35
35
–30
30
ns
50
E Width High
450
—
350
—
280
—
220
—
220
—
190
—
ns
51
E Width Low
700
—
550
—
440
—
340
—
340
—
290
—
ns
53
Data-Out Hold from Clock
High
0
—
0
—
0
—
0
—
0
—
0
—
ns
54
E Low to Data-Out Invalid
30
—
20
—
15
—
10
—
10
—
5
—
ns
55
R/
W
Asserted to Data Bus
Impedance Change
30
—
20
—
10
—
0
—
0
—
0
—
ns
56
4
HALT
(
RESET
Pulse Width
10
—
10
—
10
—
10
—
10
—
10
—
clks
57
BGACK
Negated to
AS, DS
,
R/
W
Driven
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
clks
57A
BGACK
Negated to FC,
VMA
Driven
1
—
1
—
1
—
1
—
1
—
1
—
clks
58
7
BR
Negated to
AS
,
DS
, R/
W
Driven
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
clks
58A
7
BR
Negated to FC,
AS
Driven
1
—
1
—
1
—
1
—
1
—
1
—
clks
*These specifications represent improvement over previously published specifications for the 8-, 10-, and 12.5-MHz
MC68000 and are valid only for product bearing date codes of 8827 and later.
** This frequency applies only to MC68HC000 and MC68HC001.
NOTES:
1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum
columns.
2. Actual value depends on clock period.
3. If #47 is satisfied for both
DTACK
and
BERR
, #48 may be ignored. In the absence of
DTACK
,
BERR
is an
asynchronous input using the asynchronous input setup time (#47).
4. For power-up, the MC68000 must be held in the reset state for 100 ms to allow stabilization of on-chip
circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the
processor.
5. If the asynchronous input setup time (#47) requirement is satisfied for
DTACK
, the
DTACK
asserted to data
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
6. When
AS
and R/
W
are equally loaded (
±
20;pc), subtract 5 ns from the values given in these columns.
7. The processor will negate
BG
and begin driving the bus again if external arbitration logic negates
BR
before
asserting
BGACK
.
8. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded,
BG
may
be reasserted.
9. The falling edge of S6 triggers both the negation of the strobes (
AS
and
DS
) and the falling edge of E. Either
of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the
absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of E.
10. 245 ns for the MC68008.
11. 50 ns for the MC68008
12. 50 ns for the MC68008.
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