MOTOROLA
M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
2-5
Table 2-1. Data Addressing Modes
Mode
Generation
Syntax
Register Direct Addressing
Data Register Direct
Address Register Direct
EA=Dn
EA=An
Dn
An
Absolute Data Addressing
Absolute Short
Absolute Long
EA = (Next Word)
EA = (Next Two Words)
(xxx).W
(xxx).L
Program Counter Relative
Addressing
Relative with Offset
Relative with Index and Offset
EA = (PC)+d16
EA = (PC)+d8
(d16,PC)
(d8,PC,Xn)
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
EA = (An)
EA = (An), An
←
An+N
An
ˉ
An–N, EA=(An)
EA = (An)+d16
EA = (An)+(Xn)+d8
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn)
Immediate Data Addressing
Immediate
Quick Immediate
Implied Addressing1
Implied Register
DATA = Next Word(s)
Inherent Data
#<data>
EA = SR, USP, SSP, PC,
VBR, SFC, DFC
SR,USP,SSP,PC,
VBR, SFC,DFC
NOTES: 1. The VBR, SFC, and DFC apply to the MC68010 only
EA
=
Effective Address
Dn
=
Data Register
An
=
Address Register
( )
=
Contents of
PC
=
Program Counter
d8
=
8-Bit Offset (Displacement)
d16
=
16-Bit Offset (Displacement)
N
=
1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and
the operand size is byte, N = 2 to keep the stack pointer on a word boundary.
ˉ
=
Replaces
Xn
=
Address or Data Register used as Index Register
SR
=
Status Register
USP =
User Stack Pointer
SSP =
Supervisor Stack Pointer
CP
=
Program Counter
VBR =
Vector Base Register
2.3
DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1, 8, 16, or 32 bits. The seven address
registers and the active stack pointer support address operands of 32 bits.
2.3.1 Data Registers
Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word
operands the low-order 16 bits, and long-word operands, the entire 32 bits. The least
significant bit is addressed as bit zero; the most significant bit is addressed as bit 31.