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參數(shù)資料
| 型號(hào)： | M5M4V16169DRT-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁數(shù)： | 8/64頁 |
| 文件大小： | 737K |
| 代理商： | M5M4V16169DRT-7 |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MODE DESCRIPTIONS (1)
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
8
NOP
SRAM
Power-Down
Deselect SRAM
SRAM Read
SRAM Write
No Operation. Outputs are high-impedance. All input buffers remain active.
If CMs#=Low at the rising edge of K, the SRAM enters SRAM Power Down at the next rising
edge of K. During this mode, the internal SRAM K clock becomes inactive. The Output
Buffers remain enabled and are controlled by G#. All input buffers of SRAM clocks and
SRAM addresses are inactive.
All transfer functions and input/output operations to and from the SRAM and Buffer are
disabled. This cycle is useful for output impedance control (Hi-Z,Low-Z) without G#. Output
buffers are active during this cycle for registered output mode control.
Data is read from the SRAM to the I/O pins. Addresses As0-As9 are used to select the data
to be read. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode (1 of 8) the 16-
bit word. DQCu and DQCl control the impedence (High-Z/Low-Z) of the upper and lower
bytes, respectively.
Data is written from the I/O pins to the SRAM. Addresses As0-As9 are used to select the
location to be written. As3-As9 decode the SRAM Row (=Block), and As0-As2 decode
(1of8) the 16-bit word to be written. DQCUu and DQCl control Upper and Lower byte writes,
respectively.
X
DQs
SRAM
1KX16
8X16
8X16
8X16
8X16
16bits
16bits
As3-9
1of128Decode
Ad0-9
1of4096Decode
Ad3-7
1of32
Decode
As0-2
1of8
Decode
As0-2
1of8Decode
8X16Block
8X16Block
WB1
DRAM RowDecoder
16bits
As0-2
1of8Decode
Upper Byte
Lower Byte
RB2
Upper Byte
Lower Byte
WB2
RB1
DRAM
1MX16
16bits
SRAM RowDecoder
8X16
Upper Byte
Lower Byte
Upper Byte
Lower Byte
DQ8-15
DQ0-7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DRT-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
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