參數(shù)資料
型號： M5M4V16169DRT-7
廠商： Mitsubishi Electric Corporation
英文描述： 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
中文描述： 16MCDRAM：16米（100萬字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM
文件頁數(shù)： 7/64頁
文件大?。?/td> 737K
代理商： M5M4V16169DRT-7
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
7
DQCu/l are I/OByte control signals. If G#=Low, DQCu/l have a control of output
impedence: DQCu controls upper DQs (DQ8-15) & DQCl controls lower DQs (DQ0-7).
DQCu/l also control both input data during SRAM Writes or Buffer Writes and transfer
mask during Buffer Writes. (WB1 transfer Masks for each byte are written (bits are
cleared) during Buffer Writes depending on DQCu/l inputs.)
Input
DQCl,DQCu
WE#
CC0#,CC1#
As0-As9
G#
DQ0-DQ15
VccQ
Input
Inputs
Inputs
Input
Inputs /
Outputs
Supply
Write Enable controls SRAM and Buffer read and write operations. A high on the WE#
pin causes either a Buffer Read, SRAM Read, Buffer Read Transfer and/or a Buffer
Read Transfer & Read to occur (depending on the state of the CC0# and CC1# bits).
A low on the WE# pin causes either a Buffer Write, SRAM Write, Buffer Write Transfer
and/or a Buffer Write Transfer & Write to occur (depending on the state of the CC0#
and CC1# inputs)
The Control Clock Inputs control SRAM and Buffer operations. CC0# is Low for all
Buffer Writes, Reads, and Transfers, and High for all other SRAM operations. CC1# is
high for all Buffer Read Transfers and Buffer Write Transfers , and Deselect SRAM.
SRAM Addresses are non-multiplexed, and access 1024 - 16-bit words ( configured as
128 Rows X 8 Columns X 16 Bits, where the Block Size is 8 X 16) in the SRAM array.
As0-As3 select word address within a block, and As3-As9 select the SRAM row(block).
The Output Enable is an asynchronous input. G#=high forces the outputs to high
impedence.
Output operation is either transparent, latched, or registered depending on the state of
the command register. The Data Lines for the CDRAM are asynchronously controlled
by G#.
VccQ is the DQ power supply and allows the device to operate in a mixed voltage
system (e.g., 5V data bus). As specified in the Table: Recommended Operating
Conditions, VccQ must be greater-than or equal-to the highest voltage experienced
by the data bus. For 3.3V system operation, VccQ may be tied to Vcc.
PIN DESCRIPTIONS(2)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V16169DRT-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-15 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
M5M4V16169DTP-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
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