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參數(shù)資料
| 型號(hào)： | M5M4V16169DRT-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| 中文描述： | 16MCDRAM：16米（100萬(wàn)字由16位）與16K的緩存內(nèi)存（1024字由16位）的SRAM |
| 文件頁(yè)數(shù)： | 51/64頁(yè) |
| 文件大?。?/td> | 737K |
| 代理商： | M5M4V16169DRT-7 |
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M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
MITSUBISHI LSIs
(REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
2
3
4
5
6
7
8
9
10
11
12
13
14
1
RAS#
CAS#
DTD#
Ad0-2
Ad3-11
WB1
New Data[WB1(0-7)]
Old Data
**Col
CS#
Ad0-Ad2=Low
PCG
DPD DPD
DPD DPD
ACT
DWT1
PCG
DPD
DNOP
DNOP
DPD DPD DPD
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
BW
DQ0-15
tRC
tRP
tRCD
Row
Row
tRAS
tRWL
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
DRAM
SRAM
D0
WB2
C1
C2
C3
C4
C5
C6
C7
C0
C1
C2
C3
C4
C0
DES
DRAM Write Transfer 1 (WB1->WB2->DRAM)
Buffer Write (DIN->WB1)
Please refer to next page in detail.
51
K
CMd#
SRAM operation can be freely performed.
** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).
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| M5M4V16169DRT-8 | 22182053 |
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| M5M4V64S20ATP-10 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16169DRT-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
| M5M4V16169DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM |
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