參數(shù)資料
型號： M38K29F8HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 80/126頁
文件大?。?/td> 2167K
代理商： M38K29F8HP
HARDWARE
1-38
38K2 Group User’s Manual
FUNCTIONAL DESCRIPTION
(1) Endpoint 00
Fig. 40 Structure of EP00 stage register
Fig. 41 Structure of EP00 control register 1
Fig. 42 Structure of EP00 control register 2
b7
b0
SETUP packet detection bit
Not used
SETUP00
b7:b1
1
–
1
–
EP00 stage register (EP00STG) [address 001916]
Bit name
Bit symbol
At reset
Function
H/W
S/W
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
Writing “1” to this bit causes no state change of the
status flags.
Write “0” when writing.
“0” is read when reading.
O
–: State remaining
000
0
00
0
W
R
b7
b0
Response PID bit
Not used
PID00 [1:0]
b7:b2
–
0
–
EP00 control register 1 (EP00CON1) [address 001A16]
Bit name
Bit symbol
At reset
Function
H/W
S/W
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
O
–: State remaining
000
0
00
W
R
b7
b0
Buffer enable bit
Not used
BVAL00
b7:b1
–
0
–
EP00 control register 2 (EP00CON2) [address 001B16]
Bit name
Bit symbol
At reset
Function
H/W
S/W
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
O
–: State remaining
00
0
W
R
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相關代理商/技術參數(shù)
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