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| 型號： | M38K29F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 33/126頁 |
| 文件大小： | 2167K |
| 代理商： | M38K29F8HP |
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ix
38K2 Group User’s Manual
List of figures
Fig. 2.8.1 Memory map of registers related to A-D converter .............................................. 2-72
Fig. 2.8.2 Structure of A-D control register .............................................................................. 2-72
Fig. 2.8.3 Structure of A-D conversion register 1 ................................................................... 2-73
Fig. 2.8.4 Structure of A-D conversion register 2 ................................................................... 2-73
Fig. 2.8.5 Structure of Interrupt request register 2 ................................................................. 2-74
Fig. 2.8.6 Structure of Interrupt control register 2 .................................................................. 2-74
Fig. 2.8.7 Connection diagram ................................................................................................... 2-75
Fig. 2.8.8 Related registers setting ........................................................................................... 2-75
Fig. 2.8.9 Control procedure for 8-bit read .............................................................................. 2-76
Fig. 2.8.10 Control procedure for 10-bit read .......................................................................... 2-76
Fig. 2.9.1 Memory map of registers related to watchdog timer ............................................ 2-78
Fig. 2.9.2 Structure of Watchdog timer control register ......................................................... 2-78
Fig. 2.9.3 Structure of CPU mode register .............................................................................. 2-79
Fig. 2.9.4 Watchdog timer connection and division ratio setting .......................................... 2-80
Fig. 2.9.5 Related registers setting ........................................................................................... 2-81
Fig. 2.9.6 Control procedure ....................................................................................................... 2-81
Fig. 2.10.1 Example of poweron reset circuit .......................................................................... 2-82
Fig. 2.10.2 RAM backup system ................................................................................................ 2-82
Fig. 2.11.1 Memory map of registers related to PLL .............................................................. 2-84
Fig. 2.11.2 Structure of USB control register .......................................................................... 2-84
Fig. 2.11.3 Structure of CPU mode register ............................................................................ 2-85
Fig. 2.11.4 Structure of PLL control register ........................................................................... 2-85
Fig. 2.11.5 Block diagram for frequency synthesizer circuit .................................................. 2-86
Fig. 2.11.6 Related registers setting when hardware reset ................................................... 2-87
Fig. 2.11.7 Related registers setting when stop mode ........................................................... 2-88
Fig. 2.11.8 Related registers setting when recovery from stop mode ................................. 2-89
Fig. 2.12.1 Memory map of registers related to clock generating circuit ............................ 2-90
Fig. 2.12.2 Structure of USB control register .......................................................................... 2-90
Fig. 2.12.3 Structure of CPU mode register ............................................................................ 2-91
Fig. 2.12.4 Structure of PLL control register ........................................................................... 2-91
Fig. 2.12.5 Related registers setting ......................................................................................... 2-92
Fig. 2.12.6 Related registers setting ......................................................................................... 2-94
Fig. 2.13.1 Memory map of registers related to standby function ........................................ 2-95
Fig. 2.13.2 Structure of MISRG ................................................................................................. 2-95
Fig. 2.13.3 Oscillation stabilizing time at restoration by reset input .................................... 2-97
Fig. 2.13.4 Execution sequence example at restoration by occurrence of INT0 interrupt request
................................................................................................................................... 2-99
Fig. 2.13.5 Reset input time ..................................................................................................... 2-101
Fig. 2.14.1 Memory map of flash memory version for 38K2 Group ................................... 2-103
Fig. 2.14.2 Memory map of registers related to flash memory ........................................... 2-104
Fig. 2.14.3 Structure of Flash memory control register ........................................................ 2-104
Fig. 2.14.4 Rewrite example of built-in flash memory in standard serial I/O mode ......... 2-107
Fig. 2.14.5 Connection example in standard serial I/O mode (1) ....................................... 2-108
Fig. 2.14.6 Connection example in standard serial I/O mode (2) ....................................... 2-108
Fig. 2.14.7 Connection example in standard serial I/O mode (3) ....................................... 2-109
Fig. 2.14.8 Example of rewrite system for built-in flash memory in CPU rewrite mode . 2-110
Fig. 2.14.9 CPU rewrite mode beginning/release flowchart ................................................. 2-111
CHAPTER 3 APPENDIX
Fig. 3.1.1 Output switching characteristics measurement circuit ............................................ 3-9
Fig. 3.1.2 USB output switching characteristics measurement circuit (1) for D0-, D1+/D2+ (low-speed),
D1-/D2- (full-speed) .... 3-10
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相關代理商/技術參數(shù) |
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| M38K29F8LHP | 功能描述:IC 740 MCU FLASH 32K 64LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產品培訓模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標準包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設備:欠壓檢測/復位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲器容量:192KB（96K x 16） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉換器:A/D 16x12b; D/A 2x12b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| M38K29F8LHP#U0 | 功能描述:IC 740/38K2 MCU FLASH 64-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產品培訓模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標準包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲器容量:384KB（384K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉換器:A/D 34x10b，D/A 2x8b 振蕩器型:內部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38K29F8LHP#UO | 制造商:Renesas Electronics Corporation 功能描述: |
| M38K29T-ADF | 功能描述:DEV TEMPORARY TARGET BOARD FOR M RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標準包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關產品:1-Wire? 設備 產品目錄頁面:1429 (CN2011-ZH PDF) |
| M38K29T-PAC | 制造商:Renesas Electronics Corporation 功能描述:DEV SIMPLE TOOL SYSTEM PKG FOR 38000/38K - Bulk |
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