參數(shù)資料
型號(hào): M38K29F8HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù): 116/126頁(yè)
文件大小: 2167K
代理商: M38K29F8HP
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iv
38K2 Group User’s Manual
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of 38K2 group ..................................................................................... 1-2
Fig. 2 Functional block diagram ................................................................................................. 1-3
Fig. 3 Part numbering .................................................................................................................. 1-5
Fig. 4 Memory expansion plan ................................................................................................... 1-6
Fig. 5 740 Family CPU register structure ................................................................................. 1-7
Fig. 6 Register push and pop at interrupt generation and subroutine call .......................... 1-8
Fig. 7 Structure of CPU mode register ................................................................................... 1-10
Fig. 8 Memory map diagram ..................................................................................................... 1-11
Fig. 9 Memory map of special function register (SFR) ......................................................... 1-12
Fig. 10 Port block diagram (1) ................................................................................................. 1-14
Fig. 11 Port block diagram (2) ................................................................................................. 1-15
Fig. 12 Structure of port I/O-related registers ........................................................................ 1-16
Fig. 13 Interrupt control ............................................................................................................. 1-18
Fig. 14 Structure of interrupt-related registers ....................................................................... 1-18
Fig. 15 Connection example when using key input interrupt and port P0 block diagram1-19
Fig. 16 Structure of timer X mode register ............................................................................ 1-20
Fig. 17 Timer block diagram ..................................................................................................... 1-21
Fig. 18 Block diagram of clock synchronous serial I/O ........................................................ 1-22
Fig. 19 Operation of clock synchronous serial I/O function ................................................. 1-22
Fig. 20 Block diagram of UART serial I/O .............................................................................. 1-23
Fig. 21 Operation of UART serial I/O function ....................................................................... 1-23
Fig. 22 Structure of serial I/O control registers ..................................................................... 1-25
Fig. 23 USB function overview ................................................................................................. 1-26
Fig. 24 USB Function Control Circuit (USBFCC) block diagram ......................................... 1-27
Fig. 25
USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V
≤ VCC
≤ 5.25V) ........................................................................................................................ 1-28
Fig. 26
USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V
≤ VCC
≤ 4.0V) .......................................................................................................................... 1-28
Fig. 27 Example setting of buffer area beginning address .................................................. 1-29
Fig. 28 Examples of interrupt source dependant buffer area offset address .................... 1-29
Fig. 29 USB device interrupt control ....................................................................................... 1-31
Fig. 30 USB related registers ................................................................................................... 1-32
Fig. 31 Structure of USB control register ............................................................................... 1-33
Fig. 32 Structure of USB function/HUB enable register ....................................................... 1-33
Fig. 33 Structure of USB function address register .............................................................. 1-34
Fig. 34 Structure of USB HUB address register .................................................................... 1-34
Fig. 35 Structure of Frame number register Low .................................................................. 1-34
Fig. 36 Structure of Frame number register High ................................................................. 1-34
Fig. 37 Structure of USB interrupt source enable register ................................................... 1-35
Fig. 38 Structure of USB interrupt source register ................................................................ 1-36
Fig. 39 Structure of Endpoint index register .......................................................................... 1-37
Fig. 40 Structure of EP00 stage register ................................................................................ 1-38
Fig. 41 Structure of EP00 control register 1 .......................................................................... 1-38
Fig. 42 Structure of EP00 control register 2 .......................................................................... 1-38
Fig. 43 Structure of EP00 control register 3 .......................................................................... 1-39
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