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參數(shù)資料
| 型號(hào)： | M38K29F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 34/126頁 |
| 文件大?。?/td> | 2167K |
| 代理商： | M38K29F8HP |
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38K2 Group User’s Manual
List of figures
Fig. 3.1.3 USB output switching characteristics measurement circuit (2) for D0+, D1+/D2+ (full-speed),
D1-/D2- (low-speed) ... 3-10
Fig. 3.1.4 Output switching characteristics measurement circuit .......................................... 3-19
Fig. 3.1.5 USB output switching characteristics measurement circuit (1) for D0-, D1+/D2+ (low-speed),
D1-/D2- (full-speed) .... 3-21
Fig. 3.1.6 SB output switching characteristics measurement circuit (2) for D0+, D1+/D2+ (full-speed),
D1-/D2- (low-speed) ... 3-21
Fig. 3.1.7 Timing chart (1) .......................................................................................................... 3-22
Fig. 3.1.8 Timing chart (2) .......................................................................................................... 3-23
Fig. 3.1.9 Timing chart (3) .......................................................................................................... 3-24
Fig. 3.1.10 Timing chart (4) ........................................................................................................ 3-25
Fig. 3.1.11 Timing chart (5) ........................................................................................................ 3-26
Fig. 3.1.12 Timing chart (6) ........................................................................................................ 3-27
Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-31
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-32
Fig. 3.3.3 Sequence of setting serial I/O control register again ........................................... 3-34
Fig. 3.3.4 Initialization of processor status register ................................................................ 3-38
Fig. 3.3.5 Sequence of PLP instruction execution .................................................................. 3-38
Fig. 3.3.6 Stack memory contents after PHP instruction execution ..................................... 3-38
Fig. 3.3.7 Status flag at decimal calculations .......................................................................... 3-39
Fig. 3.4.1 Selection of packages ............................................................................................... 3-41
_____________
Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-41
Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-42
Fig. 3.4.4 Wiring for CNVSS pin .................................................................................................. 3-42
Fig. 3.4.5 Wiring for the VPP pin of the flash memory version .............................................. 3-43
Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................ 3-43
Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-44
Fig. 3.4.8 Wiring for a large current signal line ...................................................................... 3-45
___________
Fig. 3.4.9 Wiring of RESET pin ................................................................................................. 3-45
Fig. 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-46
Fig. 3.4.11 Setup for I/O ports ................................................................................................... 3-46
Fig. 3.4.12 Watchdog timer by software ................................................................................... 3-47
Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-48
Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-48
Fig. 3.5.3 Structure of USB control register ............................................................................. 3-49
Fig. 3.5.4 Structure of USB function/HUB enable register ..................................................... 3-49
Fig. 3.5.5 Structure of USB function address register ............................................................ 3-49
Fig. 3.5.6 Structure of USB HUB address register ................................................................. 3-50
Fig. 3.5.7 Structure of Frame number register Low ................................................................ 3-50
Fig. 3.5.8 Structure of Frame number register High ............................................................... 3-50
Fig. 3.5.9 Structure of USB interrupt source enable register ................................................ 3-50
Fig. 3.5.10 Structure of USB interrupt source register ........................................................... 3-51
Fig. 3.5.11 Structure of Endpoint index register ...................................................................... 3-51
Fig. 3.5.12 Structure of EP00 stage register ........................................................................... 3-52
Fig. 3.5.13 Structure of EP01 set register ............................................................................... 3-52
Fig. 3.5.14 Structure of EP02 set register ............................................................................... 3-53
Fig. 3.5.15 Structure of EP03 set register ............................................................................... 3-53
Fig. 3.5.16 Structure of EP10 stage register ........................................................................... 3-54
Fig. 3.5.17 Structure of EP11 set register ............................................................................... 3-54
Fig. 3.5.18 Structure of EP00 control register 1 ..................................................................... 3-54
Fig. 3.5.19 Structure of EP01 control register 1 ..................................................................... 3-55
Fig. 3.5.20 Structure of EP02 control register 1 ..................................................................... 3-55
Fig. 3.5.21 Structure of EP03 control register 1 ..................................................................... 3-55
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| M38K29F8LHP | 功能描述:IC 740 MCU FLASH 32K 64LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標(biāo)準(zhǔn)包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲(chǔ)器容量:192KB（96K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
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