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| 型號(hào)： | M38K29F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 13/126頁(yè) |
| 文件大小： | 2167K |
| 代理商： | M38K29F8HP |
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vi
38K2 Group User’s Manual
List of figures
Fig. 96 Structure of DP1 interrupt source register ................................................................ 1-65
Fig. 97 Structure of DP1 control register ................................................................................ 1-66
Fig. 98 Structure of DP1 status register ................................................................................. 1-66
Fig. 99 Structure of DP2 interrupt source register ................................................................ 1-67
Fig. 100 Structure of DP2 control register .............................................................................. 1-68
Fig. 101 Structure of DP2 status register ............................................................................... 1-68
Fig. 102 Structure of Downstream port control register ....................................................... 1-69
Fig. 103 External bus interface ................................................................................................ 1-70
Fig. 104 Data transfer timing of memory channel ................................................................. 1-70
Fig. 105 External bus interface (EXB) pin assignment ......................................................... 1-71
Fig. 106 Block diagram of external bus interface (EXB) ...................................................... 1-72
Fig. 107 EXB related registers (1) ........................................................................................... 1-76
Fig. 108 EXB related registers (2) ........................................................................................... 1-76
Fig. 109 Structure of EXB interrupt source enable register ................................................. 1-77
Fig. 110 Structure of EXB interrupt source register .............................................................. 1-77
Fig. 111 Structure of EXB index register ................................................................................ 1-78
Fig. 112 Structure of Register window 1 ................................................................................ 1-78
Fig. 113 Structure of Register window 2 ................................................................................ 1-78
Fig. 114 Index00[low]; Structure of External I/O configuration register .............................. 1-79
Fig. 115 Index00[high]; Structure of External I/O configuration register ........................... 1-79
Fig. 116 Index01[low]; Structure of Transmit/Receive buffer register ................................. 1-80
Fig. 117 Index02[low]; Structure of Memory channel operation mode register ................. 1-80
Fig. 118 Index03[low]; Structure of Memory address counter ............................................. 1-80
Fig. 119 Index03[high]; Structure of Memory address counter ............................................ 1-81
Fig. 120 Index04[low]; Structure of End address register .................................................... 1-81
Fig. 121 Index04[high]; Structure of End address register ................................................... 1-81
Fig. 122 CPU channel receiving operation ............................................................................. 1-82
Fig. 123 CPU channel tranmitting operation .......................................................................... 1-83
Fig. 124 Memory channel receiving operation (1) ................................................................. 1-84
Fig. 125 Memory channel receiving operation (2) ................................................................. 1-85
Fig. 126 Memory channel receiving operation (3) ................................................................. 1-86
Fig. 127 Memory channel tranmitting operation (1) .............................................................. 1-87
Fig. 128 Memory channel tranmitting operation (2) .............................................................. 1-88
Fig. 129 Multichannel RAM timing diagram (no wait) ........................................................... 1-89
Fig. 130 Multichannel RAM timing diagram (one wait) ......................................................... 1-89
Fig. 131 Multichannel RAM operation example ...................................................................... 1-90
Fig. 132 Structure of A-D control register .............................................................................. 1-91
Fig. 133 10-bit A-D mode reading ........................................................................................... 1-91
Fig. 134 A-D converter block diagram .................................................................................... 1-92
Fig. 135 Block diagram of Watchdog timer ............................................................................ 1-93
Fig. 136 Structure of Watchdog timer control register .......................................................... 1-93
Fig. 137 Example of reset circuit ............................................................................................. 1-94
Fig. 138 Reset sequence .......................................................................................................... 1-94
Fig. 139 Block diagram of PLL circuit ..................................................................................... 1-95
Fig. 140 Structure of PLL control register .............................................................................. 1-96
Fig. 141 Ceramic resonator or quartz-crystal oscilltor circuit .............................................. 1-98
Fig. 142 External clock input circuit ........................................................................................ 1-98
Fig. 143 Structure of MISRG .................................................................................................... 1-98
Fig. 144 System clock generating circuit block diagram (single-chip mode) ..................... 1-98
Fig. 145 State transitions of clock ........................................................................................... 1-99
Fig. 146 Block diagram of built-in flash memory ................................................................. 1-101
Fig. 147 Structure of flash memory control register ............................................................ 1-102
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| M38K29F8LHP | 功能描述:IC 740 MCU FLASH 32K 64LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標(biāo)準(zhǔn)包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲(chǔ)器容量:192KB（96K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| M38K29F8LHP#U0 | 功能描述:IC 740/38K2 MCU FLASH 64-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲(chǔ)器容量:384KB（384K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁(yè)面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38K29F8LHP#UO | 制造商:Renesas Electronics Corporation 功能描述: |
| M38K29T-ADF | 功能描述:DEV TEMPORARY TARGET BOARD FOR M RoHS:否 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁(yè)面:1429 (CN2011-ZH PDF) |
| M38K29T-PAC | 制造商:Renesas Electronics Corporation 功能描述:DEV SIMPLE TOOL SYSTEM PKG FOR 38000/38K - Bulk |
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