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| 型號(hào)： | M38K29F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 24/126頁(yè) |
| 文件大?。?/td> | 2167K |
| 代理商： | M38K29F8HP |
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vii
38K2 Group User’s Manual
List of figures
Fig. 148 CPU rewrite mode set/release flowchart ............................................................... 1-103
Fig. 149 Program flowchart ..................................................................................................... 1-105
Fig. 150 Erase flowchart ......................................................................................................... 1-106
Fig. 151 Full status check flowchart and remedial procedure for errors ......................... 1-108
Fig. 152 Structure of ROM code protect control register ................................................... 1-109
Fig. 153 ID code store addresses ......................................................................................... 1-110
Fig. 154 Pin connection diagram in standard serial I/O mode (1) .................................... 1-114
Fig. 155 Timing for page read ................................................................................................ 1-116
Fig. 156 Timing for reading status register .......................................................................... 1-116
Fig. 157 Timing for clear status register ............................................................................... 1-117
Fig. 158 Timing for page program ......................................................................................... 1-117
Fig. 159 Timing for erase all blocks ...................................................................................... 1-118
Fig. 160 Timing for download ................................................................................................. 1-119
Fig. 161 Timing for version information output .................................................................... 1-120
Fig. 162 Timing for Boot ROM area output .......................................................................... 1-120
Fig. 163 Timing for ID check .................................................................................................. 1-121
Fig. 164 ID code storage addresses ..................................................................................... 1-121
Fig. 165 Full status check flowchart and remedial procedure for errors ......................... 1-124
Fig. 166 Example circuit application for standard serial I/O mode ................................... 1-125
Fig. 167 Definition of A-D conversion accuracy ................................................................... 1-127
Fig. 168 A-D conversion equivalent circuit ........................................................................... 1-130
Fig. 169 A-D conversion timing chart .................................................................................... 1-130
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of registers related to I/O port ........................................................... 2-2
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6) ................................................................................. 2-3
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) .................................................. 2-3
Fig. 2.1.4 Structure of Port P0 pull-up control register ............................................................ 2-4
Fig. 2.1.5 Structure of Port P5 pull-up control register ............................................................ 2-4
Fig. 2.2.1 Memory map of registers related to interrupt .......................................................... 2-8
Fig. 2.2.2 Structure of Interrupt request register 1 ................................................................... 2-8
Fig. 2.2.3 Structure of Interrupt request register 2 ................................................................... 2-9
Fig. 2.2.4 Structure of Interrupt control register 1 .................................................................... 2-9
Fig. 2.2.5 Structure of Interrupt control register 2 .................................................................. 2-10
Fig. 2.2.6 Structure of Interrupt edge selection register ........................................................ 2-10
Fig. 2.2.7 Interrupt operation diagram ....................................................................................... 2-12
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
..................................................................................................................................... 2-13
Fig. 2.2.9 Time up to execution of interrupt processing routine ........................................... 2-14
Fig. 2.2.10 Timing chart after acceptance of interrupt request ........................................... 2-14
Fig. 2.2.11 Interrupt control diagram ......................................................................................... 2-15
Fig. 2.2.12 Example of multiple interrupts ................................................................................ 2-17
Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt .
................................................................................................................................... 2-19
Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13) .
................................................................................................................................... 2-20
Fig. 2.2.15 Sequence of changing relevant register ............................................................... 2-21
Fig. 2.2.16 Sequence of check of interrupt request bit .......................................................... 2-22
Fig. 2.3.1 Memory map of registers related to timers ............................................................ 2-23
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X ................................................................... 2-23
Fig. 2.3.3 Structure of Timer 1 .................................................................................................. 2-24
Fig. 2.3.4 Structure of Timer 2, Timer X .................................................................................. 2-24
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| M38K29F8LHP | 功能描述:IC 740 MCU FLASH 32K 64LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標(biāo)準(zhǔn)包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲(chǔ)器容量:192KB（96K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤(pán) 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| M38K29F8LHP#U0 | 功能描述:IC 740/38K2 MCU FLASH 64-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲(chǔ)器容量:384KB（384K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤(pán) 產(chǎn)品目錄頁(yè)面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
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| M38K29T-PAC | 制造商:Renesas Electronics Corporation 功能描述:DEV SIMPLE TOOL SYSTEM PKG FOR 38000/38K - Bulk |
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