
viii
38K2 Group User’s Manual
List of figures
Fig. 2.3.5 Structure of Timer X mode register ......................................................................... 2-25
Fig. 2.3.6 Structure of Interrupt request register 1 ................................................................. 2-26
Fig. 2.3.7 Structure of Interrupt request register 2 ................................................................. 2-26
Fig. 2.3.8 Structure of Interrupt control register 1 .................................................................. 2-27
Fig. 2.3.9 Structure of Interrupt control register 2 .................................................................. 2-27
Fig. 2.3.10 Timers connection and setting of division ratios ................................................. 2-29
Fig. 2.3.11 Related registers setting ......................................................................................... 2-29
Fig. 2.3.12 Control procedure ..................................................................................................... 2-30
Fig. 2.3.13 Peripheral circuit example ....................................................................................... 2-31
Fig. 2.3.14 Timers connection and setting of division ratios ................................................. 2-31
Fig. 2.3.15 Related registers setting ......................................................................................... 2-32
Fig. 2.3.16 Control procedure ..................................................................................................... 2-32
Fig. 2.3.17 Judgment method of valid/invalid of input pulses ............................................... 2-33
Fig. 2.3.18 Related registers setting ......................................................................................... 2-34
Fig. 2.3.19 Control procedure ..................................................................................................... 2-35
Fig. 2.3.20 Timers connection and setting of division ratios ................................................. 2-36
Fig. 2.3.21 Related registers setting ......................................................................................... 2-37
Fig. 2.3.22 Control procedure ..................................................................................................... 2-38
Fig. 2.4.1 Memory map of registers related to Serial I/O ...................................................... 2-40
Fig. 2.4.2 Structure of Transmit/Receive buffer register ........................................................ 2-41
Fig. 2.4.3 Structure of Serial I/O status register ..................................................................... 2-41
Fig. 2.4.4 Structure of Serial I/O control register .................................................................... 2-42
Fig. 2.4.5 Structure of UART control register .......................................................................... 2-42
Fig. 2.4.6 Structure of Baud rate generator ............................................................................. 2-43
Fig. 2.4.7 Structure of Interrupt edge selection register ........................................................ 2-43
Fig. 2.4.8 Structure of Interrupt request register 2 ................................................................. 2-44
Fig. 2.4.9 Structure of Interrupt control register 2 .................................................................. 2-44
Fig. 2.4.10 Serial I/O connection examples (1) ....................................................................... 2-45
Fig. 2.4.11 Serial I/O connection examples (2) ....................................................................... 2-46
Fig. 2.4.12 Serial I/O transfer data format ............................................................................... 2-47
Fig. 2.4.13 Connection diagram ................................................................................................. 2-48
Fig. 2.4.14 Timing chart .............................................................................................................. 2-48
Fig. 2.4.15 Registers setting related to transmitting side ...................................................... 2-49
Fig. 2.4.16 Registers setting related to receiving side ........................................................... 2-50
Fig. 2.4.17 Control procedure of transmitting side .................................................................. 2-51
Fig. 2.4.18 Control procedure of receiving side ...................................................................... 2-52
Fig. 2.4.19 Connection diagram ................................................................................................. 2-53
Fig. 2.4.20 Timing chart .............................................................................................................. 2-53
Fig. 2.4.21 Registers setting related to Serial I/O .................................................................. 2-54
Fig. 2.4.22 Setting of serial I/O transmission data ................................................................. 2-54
Fig. 2.4.23 Control procedure of Serial I/O .............................................................................. 2-55
Fig. 2.4.24 Connection diagram ................................................................................................. 2-56
Fig. 2.4.25 Timing chart .............................................................................................................. 2-57
Fig. 2.4.26 Related registers setting ......................................................................................... 2-57
Fig. 2.4.27 Control procedure of master unit ........................................................................... 2-58
Fig. 2.4.28 Control procedure of slave unit ............................................................................. 2-59
Fig. 2.4.29 Connection diagram (Communication using UART) ............................................ 2-60
Fig. 2.4.30 Timing chart (using UART) ..................................................................................... 2-60
Fig. 2.4.31 Registers setting related to transmitting side ...................................................... 2-62
Fig. 2.4.32 Registers setting related to receiving side ........................................................... 2-63
Fig. 2.4.33 Control procedure of transmitting side .................................................................. 2-64
Fig. 2.4.34 Control procedure of receiving side ...................................................................... 2-65
Fig. 2.4.35 Sequence of setting serial I/O control register again ......................................... 2-67