參數(shù)資料
型號(hào)： M38K29F8HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 35/126頁
文件大?。?/td> 2167K
代理商： M38K29F8HP
xi
38K2 Group User’s Manual
List of figures
Fig. 3.5.22 Structure of EP10 control register 1 ..................................................................... 3-56
Fig. 3.5.23 Structure of EP11 control register 1 ..................................................................... 3-56
Fig. 3.5.24 Structure of EP00 control register 2 ..................................................................... 3-56
Fig. 3.5.25 Structure of EP01 control register 2 ..................................................................... 3-57
Fig. 3.5.26 Structure of EP02 control register 2 ..................................................................... 3-57
Fig. 3.5.27 Structure of EP03 control register 2 ..................................................................... 3-57
Fig. 3.5.28 Structure of EP10 control register 2 ..................................................................... 3-58
Fig. 3.5.29 Structure of EP11 control register 2 ..................................................................... 3-58
Fig. 3.5.30 Structure of EP00 control register 3 ..................................................................... 3-58
Fig. 3.5.31 Structure of EP01 control register 3 ..................................................................... 3-59
Fig. 3.5.32 Structure of EP02 control register 3 ..................................................................... 3-59
Fig. 3.5.33 Structure of EP03 control register 3 ..................................................................... 3-59
Fig. 3.5.34 Structure of EP10 control register 3 ..................................................................... 3-60
Fig. 3.5.35 Structure of EP00 interrupt source register ......................................................... 3-60
Fig. 3.5.36 Structure of EP01 interrupt source register ......................................................... 3-61
Fig. 3.5.37 Structure of EP02 interrupt source register ......................................................... 3-61
Fig. 3.5.38 Structure of EP03 interrupt source register ......................................................... 3-62
Fig. 3.5.39 Structure of EP10 interrupt source register ......................................................... 3-63
Fig. 3.5.40 Structure of EP11 interrupt source register ......................................................... 3-63
Fig. 3.5.41 Structure of EP00 byte number register ............................................................... 3-64
Fig. 3.5.42 Structure of EP01 byte number register 0 ........................................................... 3-64
Fig. 3.5.43 Structure of EP02 byte number register 0 ........................................................... 3-64
Fig. 3.5.44 Structure of EP03 byte number register 0 ........................................................... 3-65
Fig. 3.5.45 Structure of EP10 byte number register ............................................................... 3-65
Fig. 3.5.46 Structure of EP11 byte number register 0 ........................................................... 3-65
Fig. 3.5.47 Structure of EP01 byte number register 1 ........................................................... 3-66
Fig. 3.5.48 Structure of EP02 byte number register 1 ........................................................... 3-66
Fig. 3.5.49 Structure of EP03 byte number register 1 ........................................................... 3-66
Fig. 3.5.50 Structure of Prescaler12, Prescaler X .................................................................. 3-67
Fig. 3.5.51 Structure of Timer 1 ................................................................................................ 3-67
Fig. 3.5.52 Structure of Timer 2, Timer X ................................................................................ 3-68
Fig. 3.5.53 Structure of Timer X mode register ...................................................................... 3-68
Fig. 3.5.54 Structure of Transmit/Receive buffer register ...................................................... 3-69
Fig. 3.5.55 Structure of Serial I/O status register ................................................................... 3-69
Fig. 3.5.56 Structure of HUB interrupt source enable register .............................................. 3-70
Fig. 3.5.57 Structure of HUB interrupt source register ........................................................... 3-70
Fig. 3.5.58 Structure of HUB downstream port index register .............................................. 3-70
Fig. 3.5.59 Structure of DP1 interrupt source register ........................................................... 3-71
Fig. 3.5.60 Structure of DP2 interrupt source register ........................................................... 3-72
Fig. 3.5.61 Structure of DP1 control register ........................................................................... 3-73
Fig. 3.5.62 Structure of DP2 control register ........................................................................... 3-73
Fig. 3.5.63 Structure of DP1 status register ............................................................................ 3-74
Fig. 3.5.64 Structure of DP2 status register ............................................................................ 3-74
Fig. 3.5.65 Structure of EXB interrupt source enable register .............................................. 3-74
Fig. 3.5.66 Structure of EXB interrupt source register ........................................................... 3-75
Fig. 3.5.67 Structure of EXB index register ............................................................................. 3-75
Fig. 3.5.68 Structure of Register window 1 .............................................................................. 3-76
Fig. 3.5.69 Index00[low]; Structure of External I/O configuration register ......................... 3-76
Fig. 3.5.70 Index01[low]; Structure of Transmit/Receive buffer register .............................. 3-77
Fig. 3.5.71 Index02[low]; Structure of Memory channel operation mode register .............. 3-77
Fig. 3.5.72 Index03[low]; Structure of Memory address counter ........................................... 3-77
Fig. 3.5.73 Index04[low]; Structure of End address register ................................................. 3-78
Fig. 3.5.74 Structure of Register window 2 .............................................................................. 3-78
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