
Rev.1.00
Oct 26, 2004
page 53 of 79
3883 Group
SERIALIZED INTERRUPT
The serialized IRQ circuit communicates the interrupt status to the
host controller based on the Serialized IRQ Support for PCI System,
Version 6.0.
Table 17 shows the summary of serialized interrupt of 3883.
Item
The factors of serialized IRQ
The number of frame
Operation clock
Clock restart
Clock stop inhibition
Function
The numbers of serialized IRQ factor that can output simultaneously are 3.
Channel 0 (IRQ1,IRQ2)
Setting Software IRQi (i = 1, 12) request bit (bits 0, 1 of SERIRQ) to “1”.
The “1” of OBF0 and Hardware IRQi ( i=1, 12) request bit (bits 3, 4 of SERCON) to “1”.
Channel 1 (IRQx ; user selectable)
Setting the IRQx request bit (bit 7 of SERIRQ) to “1”.
The “1” of OBF1 and Hardware IRQx request bit to “1”.
Channel 0 (IRQ1, IRQ12)
Setting Software IRQ1 request bit (bit 0 of SERIRQ) to “1” or detecting “1” of OBF0 with
“1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ1 Frame.
Setting IRQ12 Software request bit (bit 1 of SERIRQ) to “1” or detecting “1” of OBF0 with
“1” of Hardware IRQ1 request bit (bit 4 of SERCON) selects IRQ12 Frame.
Channel 1 (IRQx ; user selectable)
Setting IRQx frame select bit (bit 2-6 of SERIRQ) selects IRQ 1–15 frame or extend
frame 0–10.
Synchronized with LCLK (Max. 33 MHz).
LPC clock restart enable bit (bit 1 of SERCON) enables restart owing to “L” output of CLKRUN
with the interrupt when the LPC clock has stopped or slowed down.
LPC clock stop inhibition bit (bit 2 of SERCON) enables the inhibition of clock stop control
during the IRQSER cycle when the clock tends to stop or slow down.
Table 17 Summary of serialized IRQ function