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參數(shù)資料
| 型號： | M38837G6HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 21/81頁 |
| 文件大小： | 766K |
| 代理商： | M38837G6HP |
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Rev.1.00
Oct 26, 2004
page 28 of 79
3883 Group
PULSE WIDTH MODULATION (PWM)
The 3883 group has PWM functions with 8-bit resolution and 6bit
resolution, based on a signal that is the clock input Xin or that
clock input divided by 2. PWM0 output the pulse with a 6-bit reso-
lution. PWM1, PWM2, PWM3, PWM4 and PWM5 output the pulse
with a 8-bit resolution.
Data setting
In the case of PWM0,
Set the PWM period by the PWM prescaler, and set the "H" term
of output pulse by the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 63):
PWM period = 63 X (n+1) / f (CONT) (f(CONT) = f(XIN) or 1/2f(XIN))
=7.875 X (n+1) (when f(CONT) = 8MHz)
Output pulse "H" term = PWM period X m / 63
= 0.125 X (n+1) X m
s (When f(CONT) = 8MHz)
In the case of PWM1, PWM2, PWM3, PWM4 and, PWM5,
if the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255):
PWM period = 255 X (n+1) / f (CONT) (f(CONT) = f(XIN) or 1/2f(XIN))
=31.875 X (n+1) ( (when f(CONT) = 8MHz)
Output pulse "H" term = PWM period X m / 255
=0.125 X (n+1) X m
s (When f(CONT) = 8MHz)
PWM Operation
In case of PWM0 operation , when bit 0 (PWM0 enable bit) of the
PWM control register is set to "1" , operation starts by initializing
the PWM output circuit, and pulses are output starting at an "H".
Fig. 24 PWM block diagram (PWM0)
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Other PWMs also operate by each bit of the PWM control register.
If PWM is disabled, after writing to PWM register and PWM
prescaler, the value can be read immediately.
If PWM is enabled, after writing to PWM register and PWM
prescaler, the value can be read after one period of present PWM
output.
Fig. 23 Timing of PWM period
7.875 m (n+1)
63
s
T = [7.875 (n+1)]
s
PWM0 output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz, count source
is f(XIN))
31.875 m (n+1)
255
s
T = [31.875 (n+1)]
s
PWM1,PWM2,
PWM3,PWM4,
PWM5,
output
Data bus
Count source
selection bit
“0”
“1”
PWM
prescaler pre-latch
PWM
register pre-latch
PWM
prescaler latch
PWM
register latch
Transfer control circuit
PWM register
1/2
XIN
Port P30 latch
PWM enable bit
Port P30
PWM prescaler
f(CONT)
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