參數(shù)資料
型號(hào)： M38837G6HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 41/81頁(yè)
文件大?。?/td> 766K
代理商： M38837G6HP
Rev.1.00
Oct 26, 2004
page 46 of 79
3883 Group
[LPC Control Register (LPCCON)] 002A16
SYNC output select bit (SYNCSEL)
“00”: OK
“01”: LONG & OK
“10”: Err
“11”: LONG & Err
LPC interface software reset bit (LPCSR)
“0”: Reset release (automatic)
“1”: Reset
LPC interface enable bit (LPCBEN)
“0”: P80–P86 works as port
“1”: P80–P86 works as LPC interface
Data bus buffer 0 enable bit (DBBEN0)
“0”: Data bus buffer 0 disable
“1”: Data bus buffer 0 enable
Data bus buffer 1 enable bit (DBBEN1)
“0”: Data bus buffer 1 disable
“1”: Data bus buffer 1 enable
Bits 0 and 1 of the LPC control register (LPCCON) specify the
SYNC code output.
Bit 2 of the LPC control register (LPCCON) enables the LPC inter-
face to enter the reset state by software. When LPCSR is set to
“1”, LPC interface is initialized in the same manner as the external
“L” input to LRESET pin (See Figure 50). Writing “0” to LPCSR the
reset state will be released after 1.5 cycle of
φ and this bit is
cleared to “0”.
[Data Bus Buffer Status Register i (i = 0, 1)
(DBBSTS0, DBBSTS1)] 002916, 002C16
Bits 0, 1 and 3 are read-only bits and indicate the status of the
data bus buffer. Bits 2, 4, 5, 6 and 7 are user definable flags which
can be read and written by software. The data bus buffer status
register can be read out by the host controller when bit 2 of the
slave address (A2) is “1”.
Bit 0: Output buffer full flag i (OBFi)
This bit is set to “1” when a data is written into the output data bus
buffer i and cleared to “0” when the host controller reads out the
data from the output data bus buffer i.
Bit 1: Input buffer full flag i (IBFi)
This bit is set to “1” when a data is written into the input data bus
buffer i by the host controller, and cleared to “0” when the data is
read out from the input data bus buffer i by the internal CPU.
Bit 3: XA2 flag (XA2i)
The bit 2 of slave address is latched while a data is written into the
input data bus buffer i.
[Input Data Bus Buffer i(i=0,1)
(DBBIN0, DBBIN1)] 002816, 002B16
In I/O write cycle from the host controller, the data byte of the data
phase is latched to DBBINi (i=0,1). The data of DBBINi can be
read out form the data bus buffer registers (DBB0, DBB1) address
in SFR area.
[Output Data Bus Buffer i (i = 0, 1)
(DBBOUT0, DBBOUT1)] 002816, 002B16
Writing data to data bus buffer registers (DBB0 , DBB1) address
from the internal CPU means writing to DBBOUTi (i = 0, 1). The
data of DBBOUTi (i = 1, 0) is read out from the host controller
when bit 2 of slave address (A2) is “0”.
[LPCi address register H/L
(LPC0ADL, LPC1ADL / LPC0ADH, LPC1ADH)]
0FF016 to 0FF316
The slave addresses of data bus buffer channel i(i=0,1) are defin-
able by setting LPCi address registers H/L (LPC0ADL, LPC0ADH,
LPC1ADL, LPC1ADH ). These registers can be set and cleared
any time. When the internal CPU reads LPCi address register L,
the bit 2 (A2) is fixed to “0”. The bit 2 of slave address (A2) is
latched to XA2i flag when the host controller writes the data. The
slave addresses, set in these registers, is used for comparing with
the addresses from the host controller.
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