參數(shù)資料
型號： M38837G6HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 14/81頁
文件大?。?/td> 766K
代理商： M38837G6HP
Rev.1.00
Oct 26, 2004
page 21 of 79
3883 Group
Interrupt Request
Generating Conditions
Remarks
Interrupt Source
Low
FFFC16
High
Priority
Table 8 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
Input buffer full
(IBF)
INT1
Output buffer
empty (OBE)
At reset
At detection of either rising or
falling edge of INT0 input
At input data bus buffer writing
At detection of either rising or
falling edge of INT1 input
At output data bus buffer read-
ing
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Timer X
Timer Y
Timer 1
Timer 2
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
STP release timer underflow
At falling edge of LRESET input
External interrupt
1
2
3
4
5
CNTR0
INT0
CNTR1
INT1
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of CNTR1 input
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
INT5
At detection of either rising or
falling edge of INT5 input
External interrupt
(active edge selectable)
6
7
8
9
I2C
INT2
At completion of data transfer
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
10
11
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset functions in the same way as an interrupt with the highest priority.
INT3
INT4
A/D converter
Key-on wake-up
BRK instruction
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A/D conversion
At falling of port P3 (at input) in-
put logical level AND
At BRK instruction execution
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Non-maskable software interrupt
12
13
14
15
16
FFFD16
FFFB16
FFF916
FFF716
FFF316
FFF116
FFED16
FFEF16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFFA16
FFF816
FFF616
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
LRESET
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