參數(shù)資料
型號： M38837G6HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 13/81頁
文件大?。?/td> 766K
代理商： M38837G6HP
Rev.1.00
Oct 26, 2004
page 20 of 79
3883 Group
INTERRUPTS
Interrupts occur by 15 sources among 19 sources: ten external,
eight internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt caused by the BRK instruction. An interrupt occurs when
both the corresponding interrupt request bit and interrupt enable
bit are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction interrupt cannot be disabled with any flag or
bit. The I (interrupt disable) flag disables all interrupts except the
BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
serviced according to the priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table and stored into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the inter-
rupt source selection register (INTSEL).
1. INT0 or Input buffer full
2. INT1 or Output buffer empty
3. Timer 2 or INT5
4. CNTR0 or INT0
5. CNTR1 or INT1
6. A/D conversion or Key-on wake-up
External Interrupt Pin Selection
The external interrupt sources of INT2, INT3, and INT4 can be se-
lected from either input pin from INT20, INT30, INT40 or input pin
from INT21, INT31, INT41 by the INT2, INT3, INT4 interrupt switch
bit (bit 4 of PCTL2).
s Notes
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16); Timer XY mode register (address
002316)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register (address
003916)
When setting input pin of external interrupts INT2, INT3 and INT4
Related register: INT2, INT3, INT4 interrupt switch bit of Port con-
trol register 2 (bit 4 of address 002F16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the active edge selection bit or the interrupt source selection
bit to “1”.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
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