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2. APPLICATION
MITSUBISHI MICROCOMPUTER
3819 Group
2.9 Clock generating circuit
3819 Group USER’S MANUAL
Control procedure : Set the related registers in the order shown below to prepare for a power failure.
Fig. 2.9.19 Control procedure (1) [Counting without clock errors during a power failure]
Middle-speed mode
Select the XCIN-XCOUT oscillating function
Main clock division ratio : select the high-speed
mode
Set for being count the base and 1 second
counters during the Timer 1 interrupts.
In the normal power state, these software
counters generate one second.
Timer 1 count source : f(X CIN)
Timer 1 interrupt : Disabled
Internal system clock : select the low-speed
mode f(X CIN).
Main clock f(XIN) : Stopped
Set for generating the Timer 3 interrupts every
second.
Generate 1 second by the hardware timer during
a power failure.
Timer 3 interrupt : Enabled
Generate the Timer 3 interrupts every second
(recover from a wait mode)
Note : Do not switch at the same time.
N
Y
Recovery processing from a power failure
Execute the WIT instruction
N
Y
Detect a power failure?
ICON2(Address:3F 16), bit0
1
~
RESET
Initialization
CPUM (Address:3B 16), bit4
1
CPUM
T1
T12M
T34M
IREQ1
IREQ2
Base counter
1second counter
ICON1
(Address:3B16), bit6
(Address:2016)
(Address:2816)
(Address:2916), bit6, bit0
(Address:2916), bit2
(Address:3C16), bit6
(Address:3D16), bit0
(Internal RAM)
(Address:3E16), bit6
0
64–1
0016
0
1
0
256–1
16–1
1
~
(Address:2816), bit2
(Address:3E16), bit6
(Address:3B16), bit7
(Address:3B16), bit5
(Address:3C16), bit6
(Address:3D16), bit0
(Address:2016)
(Address:2116)
(Address:2216)
T12M
ICON1
CPUM
IREQ1
IREQ2
T1
T2
T3
1
0
1(Note)
0
8–1
256–1
16–1
Be concluded the condition
recovered from a power failure?
q