參數(shù)資料
型號(hào): M37754S4CGP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 99/114頁(yè)
文件大小: 1116K
代理商: M37754S4CGP
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85
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timer B input (Count input in event counter mode)
Symbol
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
Parameter
Limits
Min.
80
40
160
80
Max.
ns
Unit
Limits
Symbol
Parameter
Min.
Max.
Unit
16
× 109
f(XIN)
8
× 109
f(XIN)
8
× 109
f(XIN)
4
× 109
f(XIN)
8
× 109
f(XIN)
4
× 109
f(XIN)
(400)
(320)
(200)
(160)
(200)
(160)
f(XIN)
≤ 40 MHz
f(XIN)
≤ 25 MHz
f(XIN)
≤ 40 MHz
f(XIN)
≤ 25 MHz
f(XIN)
≤ 40 MHz
f(XIN)
≤ 25 MHz
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
ns
Timer B input (Pulse period measurement mode)
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN)
≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
Limits
Symbol
Parameter
Min.
Max.
Unit
16
× 109
f(XIN)
8
× 109
f(XIN)
8
× 109
f(XIN)
4
× 109
f(XIN)
8
× 109
f(XIN)
4
× 109
f(XIN)
(400)
(320)
(200)
(160)
(200)
(160)
f(XIN)
≤ 40 MHz
f(XIN)
≤ 25 MHz
f(XIN)
≤ 40 MHz
f(XIN)
≤ 25 MHz
f(XIN)
≤ 40 MHz
f(XIN)
≤ 25 MHz
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
ns
Timer B input (Pulse width measurement mode)
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN)
≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
tc(AD)
tw(ADL)
Symbol
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Parameter
Min.
1000
125
Limits
Max.
ns
Unit
A-D trigger input
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PDF描述
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