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參數(shù)資料
| 型號(hào)： | M37754S4CGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 86/114頁(yè) |
| 文件大小： | 1116K |
| 代理商： | M37754S4CGP |
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73
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor modes are explained bellow.
Fig. 86 External memory area for each mode
Microprocessor
mode
Memory expansion
mode
FFFFFF16
ROM
RAM
SFR
8016
1616 to 1916
216 to 916
The shaded area is the external memory area.
(1) Single-chip mode [00]
The microcomputer enters the single-chip mode by connecting the
CNVss pin to Vss and starting from reset. Ports P0 to P4, P10 and
P11 all function as normal I/O ports. Port P42 can output clock
source
φ 1 by setting bit 7 of the processor mode register 0 to “1”.
_
_ ___
_
In this mode, enable signal E is output from pin E/RD. Signal E out-
put can be stopped by setting the signal output disable select bit (bit
4 of particular function select register 1) to “1”, and it is possible to
switch the output to “L” level. Table 8 shows the function of the signal
output disable select bit’s function.
(2) Memory expansion mode [01]
The microcomputer enters the memory expansion mode by setting
the processor mode bits to “01” after connecting the CNVss pin to
Vss and starting from reset.
_ __
___
Pin E/RD becomes the RD output pin. RD is an read signal, and read
is performed during it is “L” level. When the internal memory area is
___
read, the RD output can be fixed to “H” by setting the signal output
disable select bit to “1”.
Ports P0, P1 and P2 become the output pins of addresses A0 to A19
and A23, and their I/O port function are lost.
Port P10 becomes I/O pins of data D0 to D7 and loses its I/O port
function. When the BYTE pin’s level is “L”, those pins function as
data I/O pins at an even address. When the level is “H”, those pins
function as data I/O pins at even and odd addresses. However, if an
internal memory area is read, external data is not input
When the BYTE pin’s level is “H” and the multiplex bus select bit (bit
5 of chip select area register; Figure 88) is “1”, port P10 functions as
follows during the bus cycle in which the external memory area cor-
___
responding to the chip select CS4 are accessed:
Output pins of addresses LA0 to LA7, same as low-order addresses
___
A0 to A7, during “H” of RD or WR.
___
Data input/output pins at even and odd addresses during “L” of RD
___
or WR.
That is, it functions as a multiplex bus during that bus cycle.
Port P11 has two functions depending on the level of the BYTE pin.
When the BYTE pin level is “L”, those pins function as data D8 to D15
I/O pins at an odd address. The I/O port function is lost. However, if
an internal memory area is read, external data is not input. When the
BYTE pin level is “H”, port P11 functions as a programmable port
P11 similarly in the single-chip mode.
___
____
_____
Ports P30, P31, P32, and P33 become WR, BHE, ALE, and HLDA
output pins respectively and lose their I/O port functions.
___
WR is a write signal which indicates a write when it is “L”.
____
BHE is a byte-high-enable signal which indicates that an odd ad-
dress is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed si-
____
multaneously when address A0 is “L” and BHE is “L”.
ALE is an address-latch-enable signal. The latch is open while ALE
is “H”, so that the address signal passes through; the address is held
while ALE is “L”.
_____
HLDA is a hold-acknowledge signal and is used to indicate to the
_____
external that the microcomputer accepts HOLD input and enters
Hold state.
_____
____
Ports P40 and P41 become HOLD and RDY input pins, respectively,
and their I/O port function are lost.
_____
HOLD is a hold-request signal. It is an input signal used to make the
_____
microcomputer enter Hold state. HOLD input is accepted when the
φ BIU has fallen from “H” to “L” level while the bus is not used. In Hold
state,
φ CPU stops at “L”. A0 to A19, A23, D0 to D7, D8 to D15 (at BYTE
___ ___
____
= “L”), RD, WR and BHE become floating then. These pins become
_____
floating one cycle of
φ BIU later than HLDA signal becomes “L” level.
When terminating Hold state, these pins are terminated from floating
_____
state one cycle of
φ BIU later than HLDA signal becomes “H” level.
____
RDY is a ready signal. When this signal goes “L”,
φ CPU and φ BIU
____
stop at “L”. RDY is used when a slow external memory is connected
and others.
Port P42 becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes the clock
φ 1 output pin when bit
____
7 is “1”. The
φ 1 output is independent of RDY and does not stop
____
even when
φ CPU and φ BIU stop owing to “L” input to the RDY pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37754S4CHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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