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參數(shù)資料
| 型號： | M37754S4CGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 73/114頁 |
| 文件大小： | 1116K |
| 代理商： | M37754S4CGP |
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61
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 74 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf32/Pf32, which is obtained by di-
viding the peripheral devices’ clock Pf2 by 16; or clock Wf512/Pf512,
which is obtained by doing it by 256. The watchdog timer frequency
select register shown in Figure 75 selects which clock is counted.
Wf512/Pf512 is selected when its contents are “0”, and Wf32/Pf32 is
selected when they are “1”. They are cleared to “0” after reset.
The watchdog timer clock select bit (bit 3 of particular function select
register 1; Figure 62) selects use of clock Wf512/Wf32 or Pf512/Pf32
as the clock source of watchdog timer. When selecting Wf512/Wf32,
the clock source of watchdog timer (Wf512/Wf32) is not active during
Hold state. When selecting Pf512/Pf32, the clock source of watchdog
timer (Pf512/Pf32) is active during Hold state, however, current con-
sumption can be reduced. It is because the Wf512/Wf32 division cir-
cuit stops.
FFF16 is set in the watchdog timer when “L” or 2Vcc is applied to the
______
RESET pin, STP instruction is executed, data is written to the watch-
dog timer, or the most significant bit of the watchdog timer becomes
“0”.
After FFF16 is set in the watchdog timer, when the watchdog timer
counts the clock source by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF16 is set again in the watchdog timer.
Normally, a program is written so that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program ex-
ecution and others, the most significant bit of the watchdog timer
becomes “0” and an interrupt is generated.
The microcomputer can be reset by writing “1” to bit 3 (software re-
set bit) of processor mode register 0 in the interrupt routine, de-
scribed in Figure 16 in the interrupt section, and generating a reset
pulse.
______
The watchdog timer stops its function when the RESET pin voltage
is raised to double the Vcc voltage.
The watchdog timer can also be used to return from when the clock
is stopped by the STP instruction. Refer to the section on the clock
generating circuit for more details.
The watchdog timer also becomes Hold state during Hold state and
the clock input to it is stopped.
Watchdog timer frequency select register
Watchdog timer clock select bit
Write to watchdog timer
STP instruction
S
R
Q
2Vcc
detection
Wachdog timer
Set FFF16
RESET
1/16
Wf32
Wf512
Clock source for peripheral
devices
1/8
1/2
1/8
Pf32
Pf512
Pf16
Hold request
Address 6016
Pf16
STP return select bit
Fig. 74 Watchdog timer block diagram
76543210
Watchdog timer frequency
select register
0 : W f512 or Pf512 selected
1 : W f32 or Pf32 selected
This bit must be fixed to “0.”
6543210
0
Address
6116
Fig. 75 Watchdog timer frequency select register bit configuration
Pf2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37754S4CHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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